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1. 发明授权

US06635537B2 Method of fabricating gate oxide 有权
公开(公告)号：US06635537B2
公开(公告)日：2003-10-21
申请号：US09828544
申请日：2001-04-06
申请人： Tong-Hsin Lee , Shih-Chien Hsu , Chang-Chi Huang , Cheng-Tung Huang , Sheng-Hao Lin
发明人： Tong-Hsin Lee , Shih-Chien Hsu , Chang-Chi Huang , Cheng-Tung Huang , Sheng-Hao Lin
IPC分类号： H01L21336
CPC分类号： H01L21/76224 , H01L21/823462 , H01L21/823481
摘要： A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench. A gate oxide is formed on the substrate with a thickness larger at the top edge corner of the trench than elsewhere.

2. 发明授权

US06569726B1 Method of manufacturing MOS transistor with fluoride implantation on silicon nitride etching stop layer 有权
标题翻译：在氮化硅蚀刻停止层上制造具有氟化物注入的MOS晶体管的方法
公开(公告)号：US06569726B1
公开(公告)日：2003-05-27
申请号：US10154604
申请日：2002-05-22
申请人： Tong-Hsin Lee , Terry Chung-Yi Chen
发明人： Tong-Hsin Lee , Terry Chung-Yi Chen
IPC分类号： H01L218238
CPC分类号： H01L29/665 , H01L21/265 , H01L27/11 , Y10S438/919
摘要： A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013 ˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.
摘要翻译：一种制造MOS晶体管的方法。提供了具有栅极氧化物层，栅电极和附着到栅电极的侧壁的间隔物的衬底。进行源极/漏极（S / D）注入以在栅电极的每一侧上的衬底中形成源极/漏极区域。进行自对准硅化物（硅化物）工艺以在暴露的栅极电极和源极/漏极区域上形成自对准的硅化物层。在衬底上形成用作蚀刻停止层的氮化硅层。氮化硅蚀刻停止层的氟化物覆盖层注入使用约5×10 13〜5×10 14 cm -2的注入剂量和2KeV〜5KeV之间的注入能级进行。注入氮化硅层的氟化物捕获氮化硅层内的氢，从而降低自由氢浓度并增加MOS晶体管的阈值电压稳定性。

3. 发明授权

US6090698A Fabrication method for an insulation structure having a low dielectric constant 失效
标题翻译：具有低介电常数的绝缘结构的制造方法
公开(公告)号：US6090698A
公开(公告)日：2000-07-18
申请号：US359518
申请日：1999-07-23
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7682
摘要： A low-dielectric constant insulation structure is described in which low-dielectric constant insulation layers and silicon oxide layers are alternately stacked on the substrate to form a stacked insulation layer. A required pattern is then etched in the stacked insulation layer followed by a selective etching to remove a portion of the low dielectric insulation layer to form, starting from the sidewall of the stacked insulation layer and extending inwardly, a plurality of recessed regions. A sputtering deposition and etching-back are further conducted on the sidewall of the stacked insulation layer to form a sidewall spacer to enclose the already formed recessed regions. A plurality of air-gaps is formed in the stacked insulation layer to establish a low dielectric insulation structure.
摘要翻译：描述了一种低介电常数绝缘结构，其中低介电常数绝缘层和氧化硅层交替堆叠在基板上以形成层叠绝缘层。然后在堆叠的绝缘层中蚀刻所需的图案，然后进行选择性蚀刻以去除低介电绝缘层的一部分，以从堆叠的绝缘层的侧壁开始并向内延伸多个凹陷区域。在层叠绝缘层的侧壁上进一步进行溅射沉积和蚀刻，以形成侧壁间隔物以封闭已经形成的凹陷区域。在堆叠的绝缘层中形成多个空气隙以建立低介电绝缘结构。

4. 发明授权

US6069032A Salicide process 失效
标题翻译：自杀过程
公开(公告)号：US6069032A
公开(公告)日：2000-05-30
申请号：US375619
申请日：1999-08-17
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423
CPC分类号： H01L29/66575 , H01L21/28114 , H01L29/665 , H01L29/66545 , H01L21/28052 , H01L29/42376
摘要： A salicide process is described. The edge of a gate are etched to form a reversed T-shaped gate that is then self-aligned by a silicide film. This etching step can be performed by using a silicon oxynitride layer as an etching mask over the gate.
摘要翻译：描述了一个自杀过程。蚀刻栅极的边缘以形成反向的T形栅极，然后通过硅化物膜自对准。该蚀刻步骤可以通过在栅极上使用氮氧化硅层作为蚀刻掩模来进行。

5. 发明授权

US06214741B1 Method of fabricating a bit line of flash memory 有权
标题翻译：制造闪存位线的方法
公开(公告)号：US06214741B1
公开(公告)日：2001-04-10
申请号：US09434712
申请日：1999-11-05
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L2100
CPC分类号： H01L29/7881 , H01L29/42324 , H01L29/66825
摘要： A method of fabricating a bit line of a flash memory. A silicon-on-insulator (SOI) has a buried oxide layer therein and a silicon layer thereon. A patterned hard mask layer is formed on the silicon layer. The exposed silicon layer and the buried oxide layer thereunder are removed to form a bit line opening while using the hard mask layer as a mask. A conformal lightly doped polysilicon layer is formed over the substrate. A heavily doped polysilicon layer is formed over the substrate and filling the bit line opening. The lightly doped polysilicon layer and the heavily doped polysilicon layer are removed until arriving at the silicon layer to form a bit line. The hard mask layer is then removed.
摘要翻译：一种制造闪存的位线的方法。绝缘体上硅（SOI）在其中具有掩埋氧化层，其上有硅层。在硅层上形成图案化的硬掩模层。在使用硬掩模层作为掩模的同时，去除暴露的硅层和其下的掩埋氧化物层以形成位线开口。在衬底上形成共形轻掺杂多晶硅层。在衬底上形成重掺杂多晶硅层并填充位线开口。去除轻掺杂多晶硅层和重掺杂多晶硅层，直到到达硅层以形成位线。然后去除硬掩模层。

6. 发明授权

US6060361A Method for preventing dopant diffusion in dual gate device 失效
标题翻译：防止双栅极器件掺杂物扩散的方法
公开(公告)号：US6060361A
公开(公告)日：2000-05-09
申请号：US206187
申请日：1998-12-04
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L21/336
CPC分类号： H01L21/28061 , H01L21/823842 , H01L29/4941
摘要： A method for preventing the diffusion of dopants in a dual gate device includes the steps of providing a semiconductor substrate having wells and isolating structures thereon, and then forming a gate oxide layer over the well regions. Thereafter a polysilicon layer is formed over the gate oxide layer, and then a first conductive layer is formed over the polysilicon layer. Subsequently, a plasma treatment using gaseous nitrogen or gaseous ammonia is conducted to form a barrier layer. Finally, a second conductive layer is formed over the barrier layer.
摘要翻译：一种用于防止掺杂剂在双栅极器件中的扩散的方法包括以下步骤：提供具有阱并在其上隔离结构的半导体衬底，然后在阱区上形成栅极氧化物层。此后，在栅极氧化物层上形成多晶硅层，然后在多晶硅层上形成第一导电层。随后，进行使用气态氮或气态氨的等离子体处理以形成阻挡层。最后，在阻挡层上形成第二导电层。

7. 发明授权

US06664172B2 Method of forming a MOS transistor with improved threshold voltage stability 失效
公开(公告)号：US06664172B2
公开(公告)日：2003-12-16
申请号：US09683578
申请日：2002-01-22
申请人： Tong-Hsin Lee , Chung-Yi Chen
发明人： Tong-Hsin Lee , Chung-Yi Chen
IPC分类号： H01L21425
CPC分类号： H01L21/425
摘要： The gate for at least one transistor is formed on the surface of the semiconductor substrate and the gate is utilized as a mask to form a lightly doped drain of the transistor. A low thermal budget deposition process is performed to form a silicon nitride layer on the surface or the semiconductor substrate. An ion implantation process is performed to implant fluorine atoms into the silicon nitride layer. After that, an etching process is performed to form a spacer in the periphery of the gate. Finally, a source/drain of the transistor is formed. The implanted fluorine atoms bond with the hydrogen atoms and keep them from becoming interface trapped charges. This increases the threshold voltage stability of the transistor.

8. 发明授权

US06300238B1 Method of fabricating node contact opening 失效
标题翻译：节点接触开口的制作方法
公开(公告)号：US06300238B1
公开(公告)日：2001-10-09
申请号：US09390104
申请日：1999-09-03
申请人： Tong-Hsin Lee , Terry Chung-Yi Chen
发明人： Tong-Hsin Lee , Terry Chung-Yi Chen
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814
摘要： A fabrication method of a node contact opening involves forming a first insulating layer on the substrate, in which a bit line, which contacts the substrate, is formed on the first insulating layer. A conformal second insulating layer that serves as an etching stop layer is formed after the formation of bit line. A third insulating layer is then formed to isolate the subsequently formed capacitor and bit line. A pattern mask is formed on the third insulating layer, while a pattern of the pattern mask is transferred into the third insulating layer, so that an opening is formed in the third insulating layer. After the second insulating layer in the opening is removed, a spacer is formed on a sidewall of the opening. With the pattern mask and the spacer serving as an etching mask, the first insulating layer below the bit line is etched until the opening is extended through to the substrate, so that a contact opening is formed.
摘要翻译：节点接触开口的制造方法包括在衬底上形成第一绝缘层，其中在第一绝缘层上形成接触衬底的位线。在形成位线之后形成用作蚀刻停止层的保形第二绝缘层。然后形成第三绝缘层以隔离随后形成的电容器和位线。在第三绝缘层上形成图形掩模，同时将图案掩模的图案转移到第三绝缘层中，从而在第三绝缘层中形成开口。在开口中的第二绝缘层被去除之后，在开口的侧壁上形成间隔物。利用图案掩模和间隔件作为蚀刻掩模，蚀刻位线下方的第一绝缘层直到开口延伸到基板，从而形成接触开口。

9. 发明授权

US06174782B1 Method of fabricating lower electrode of capacitor 有权
标题翻译：制造电容器下电极的方法
公开(公告)号：US06174782B1
公开(公告)日：2001-01-16
申请号：US09406505
申请日：1999-09-28
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L2120
CPC分类号： H01L27/10855 , H01L28/91
摘要： The invention provides a method for fabricating a lower electrode of the capacitor, which method provides a substrate formed with source/drain (S/D) regions. Landing pads are formed on the substrate for connecting to source/drain regions. A dielectric layer is formed on the substrate to cover the landing pads. A stop layer, an insulating layer, and a mask layer are formed in sequence on the dielectric layer. The insulating layer and the mask layer are patterned to form a capacitor opening that exposes the stop layer, followed by forming a spacer on a sidewall of the capacitor opening. With the patterned mask layer and the spacer serving as an etching mask, the stop layer and the dielectric layer are etched in sequence to form a node contact opening which exposes the landing pad, wherein the capacitor opening and the node contact opening form a damascene contact opening. A conformal conducting layer is formed for filling the damascene contact opening, and planarized by CMP. Consequently, the insulating layer is removed by etching to complete the manufacture of lower electrodes of the capacitor.
摘要翻译：本发明提供一种用于制造电容器的下电极的方法，该方法提供形成有源极/漏极（S / D）区域的衬底。在衬底上形成着接点用于连接到源极/漏极区域。在基板上形成介电层以覆盖着陆焊盘。在电介质层上依次形成阻挡层，绝缘层和掩模层。将绝缘层和掩模层图案化以形成暴露停止层的电容器开口，随后在电容器开口的侧壁上形成间隔物。利用图案化的掩模层和用作蚀刻掩模的间隔物，依次蚀刻阻挡层和电介质层以形成暴露着陆焊盘的节点接触开口，其中电容器开口和节点接触开口形成镶嵌接触开放形成用于填充镶嵌接触开口的共形导电层，并通过CMP平坦化。因此，通过蚀刻去除绝缘层以完成电容器的下电极的制造。

10. 发明授权

US06169017A Method to increase contact area 失效
标题翻译：增加接触面积的方法
公开(公告)号：US06169017A
公开(公告)日：2001-01-02
申请号：US09447858
申请日：1999-11-23
申请人： Tong-Hsin Lee
发明人： Tong-Hsin Lee
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/42376 , H01L29/4983 , H01L29/4991 , H01L29/6659
摘要： A fabrication method to increase the gate contact area is described, in which a conformal first sacrificial layer is formed on the silicon substrate and the gate structure. A second sacrificial layer is further formed on the silicon substrate, wherein the surface of the second sacrificial layer is lower than the top of the polysilicon gate by a certain thickness. The exposed sacrificial layer is then removed, followed by forming a conformal silicon layer to cover the silicon substrate. A spacer is further formed on a sidewall of the gate structure. Using the spacer as a mask, the exposed polysilicon layer is removed to form a side-wing polysilicon layer on both sides of the gate to increase the contact area of the gate. The spacer, the second sacrificial layer and the first sacrificial layer are then removed. A silicidation process is further conducted to form a silicide layer on the gate structure and the two side-wing polysilicon layer to lower the gate contact resistance.
摘要翻译：描述了增加栅极接触面积的制造方法，其中在硅衬底和栅极结构上形成共形的第一牺牲层。第二牺牲层进一步形成在硅衬底上，其中第二牺牲层的表面比多晶硅栅极的顶部低一定厚度。然后去除暴露的牺牲层，随后形成覆盖硅衬底的共形硅层。间隔件还形成在栅极结构的侧壁上。使用间隔物作为掩模，去除暴露的多晶硅层，以在栅极的两侧形成侧翼多晶硅层，以增加栅极的接触面积。然后移除间隔物，第二牺牲层和第一牺牲层。进一步进行硅化处理以在栅极结构和两个侧翼多晶硅层上形成硅化物层以降低栅极接触电阻。

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