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1. 发明授权

US08386664B2 Reducing runtime coherency checking with global data flow analysis 有权
标题翻译：通过全局数据流分析减少运行时一致性检查
公开(公告)号：US08386664B2
公开(公告)日：2013-02-26
申请号：US12125167
申请日：2008-05-22
申请人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
发明人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
IPC分类号： G06F13/28 , G06F12/00 , G06F13/00 , G06F21/00
CPC分类号： G06F8/433
摘要： Reducing runtime coherency checking using global data flow analysis is provided. A determination is made as to whether a call is for at least one of a DMA get operation or a DMA put operation in response to the call being issued during execution of a compiled and optimized code. A determination is made as to whether a software cache write operation has been issued since a last flush operation in response to the call being the DMA get operation. A DMA get runtime coherency check is then performed in response to the software cache write operation being issued since the fast flush operation.
摘要翻译：提供了使用全局数据流分析减少运行时一致性检查。确定在执行编译和优化的代码期间是否响应于正在发出的呼叫而进行DMA获取操作或DMA置位操作中的至少一个的呼叫。确定自上一次刷新操作以来是否已经发出软件缓存写入操作，以响应于该调用是DMA获取操作。然后执行DMA获得运行时一致性检查，以响应快速刷新操作后发出的软件缓存写入操作。

2. 发明授权

US08281295B2 Computer analysis and runtime coherency checking 失效
标题翻译：计算机分析和运行时一致性检查
公开(公告)号：US08281295B2
公开(公告)日：2012-10-02
申请号：US12125982
申请日：2008-05-23
申请人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
发明人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/433
摘要： Compiler analysis and runtime coherency checking for reducing coherency problems is provided. Source code is analyzed to identify at least one of a plurality of loops that contains a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by at least one of a software controlled cache or a direct buffer. A determination is made as to whether there is a data dependence between the memory reference and at least one reference from at least one of other direct buffers or other software controlled caches in response to an indication that the memory reference is an access to the global memory that should be handled by either the software controlled cache or the direct buffer. A direct buffer transformation is applied to the memory reference in response to a negative indication of the data dependence.
摘要翻译：提供了编译器分析和运行时相关性检查，以减少相关性问题。分析源代码以识别包含存储器引用的多个循环中的至少一个。确定存储器引用是否是对由软件控制的高速缓存或直接缓冲器中的至少一个来处理的全局存储器的访问。确定响应于存储器引用是对全局存储器的访问的指示，确定存储器引用与来自其他直接缓冲器或其他软件控制的高速缓存中的至少一个的至少一个引用之间是否存在数据依赖性应由软件控制的缓存或直接缓冲区来处理。响应于数据依赖性的负指示，将直接缓冲器变换应用于存储器引用。

3. 发明申请

US20090293048A1 Computer Analysis and Runtime Coherency Checking 失效
标题翻译：计算机分析与运行时一致性检查
公开(公告)号：US20090293048A1
公开(公告)日：2009-11-26
申请号：US12125982
申请日：2008-05-23
申请人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
发明人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/433
摘要： Compiler analysis and runtime coherency checking for reducing coherency problems is provided. Source code is analyzed to identify at least one of a plurality of loops that contains a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by at least one of a software controlled cache or a direct buffer. A determination is made as to whether there is a data dependence between the memory reference and at least one reference from at least one of other direct buffers or other software controlled caches in response to an indication that the memory reference is an access to the global memory that should be handled by either the software controlled cache or the direct buffer. A direct buffer transformation is applied to the memory reference in response to a negative indication of the data dependence.
摘要翻译：提供了编译器分析和运行时相关性检查，以减少相关性问题。分析源代码以识别包含存储器引用的多个循环中的至少一个。确定存储器引用是否是对由软件控制的高速缓存或直接缓冲器中的至少一个来处理的全局存储器的访问。确定响应于存储器引用是对全局存储器的访问的指示，确定存储器引用与来自其他直接缓冲器或其他软件控制的高速缓存中的至少一个的至少一个引用之间是否存在数据依赖性应由软件控制的缓存或直接缓冲区来处理。响应于数据依赖性的负指示，将直接缓冲器变换应用于存储器引用。

4. 发明申请

US20090293047A1 Reducing Runtime Coherency Checking with Global Data Flow Analysis 有权
标题翻译：使用全局数据流分析减少运行时一致性检查
公开(公告)号：US20090293047A1
公开(公告)日：2009-11-26
申请号：US12125167
申请日：2008-05-22
申请人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
发明人： Tong Chen , Haibo Lin , John K. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/433
摘要： Reducing runtime coherency checking using global data flow analysis is provided. A determination is made as to whether a call is for at least one of a DMA get operation or a DMA put operation in response to the call being issued during execution of a compiled and optimized code. A determination is made as to whether a software cache write operation has been issued since a last flush operation in response to the call being the DMA get operation. A DMA get runtime coherency check is then performed in response to the software cache write operation being issued since the last flush operation.
摘要翻译：提供了使用全局数据流分析减少运行时一致性检查。确定在执行编译和优化的代码期间是否响应于正在发出的呼叫而进行DMA获取操作或DMA置位操作中的至少一个的呼叫。确定自上一次刷新操作以来是否已经发出软件缓存写入操作，以响应于该调用是DMA获取操作。然后执行DMA获得运行时一致性检查，以响应自上次刷新操作以来发出的软件缓存写入操作。

5. 发明授权

US08776034B2 Dynamically maintaining coherency within live ranges of direct buffers 失效
标题翻译：在直接缓冲区的生存范围内动态维护一致性
公开(公告)号：US08776034B2
公开(公告)日：2014-07-08
申请号：US13584356
申请日：2012-08-13
申请人： Tong Chen , John K. O'Brien , Tao Zhang
发明人： Tong Chen , John K. O'Brien , Tao Zhang
IPC分类号： G06F9/45 , G06T13/00 , H04L12/50
CPC分类号： G06F8/4442
摘要： Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.
摘要翻译：提供了减少数据处理系统中的一致性问题。要编译的源代码被接收和分析以识别包含存储器引用的多个循环中的至少一个循环。确定存储器引用是否是应该由直接缓冲器处理的全局存储器的访问。响应于指示存储器引用是对由直接缓冲器处理的全局存储器的访问，存储器引用被标记用于直接缓冲器转换。然后将直接缓冲区变换应用于存储器引用。

6. 发明授权

US08285670B2 Dynamically maintaining coherency within live ranges of direct buffers 失效
标题翻译：在直接缓冲区的生存范围内动态维护一致性
公开(公告)号：US08285670B2
公开(公告)日：2012-10-09
申请号：US12177507
申请日：2008-07-22
申请人： Tong Chen , John K. O'Brien , Tao Zhang
发明人： Tong Chen , John K. O'Brien , Tao Zhang
IPC分类号： G06F7/00
CPC分类号： G06F8/4442
摘要： Reducing coherency problems in a data processing system is provided. Source code that is to be compiled is received and analyzed to identify at least one of a plurality of loops that contain a memory reference. A determination is made as to whether the memory reference is an access to a global memory that should be handled by a direct buffer. Responsive to an indication that the memory reference is an access to the global memory that should be handled by the direct buffer, the memory reference is marked for direct buffer transformation. The direct buffer transformation is then applied to the memory reference.
摘要翻译：提供了减少数据处理系统中的一致性问题。要编译的源代码被接收和分析以识别包含存储器引用的多个循环中的至少一个循环。确定存储器引用是否是应该由直接缓冲器处理的全局存储器的访问。响应于指示存储器引用是对由直接缓冲器处理的全局存储器的访问，存储器引用被标记用于直接缓冲器转换。然后将直接缓冲区变换应用于存储器引用。

7. 发明申请

US20100088673A1 Optimized Code Generation Targeting a High Locality Software Cache 失效
标题翻译：针对高位置软件缓存的优化代码生成
公开(公告)号：US20100088673A1
公开(公告)日：2010-04-08
申请号：US12246602
申请日：2008-10-07
申请人： Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4442
摘要： Mechanisms for optimized code generation targeting a high locality software cache are provided. Original computer code is parsed to identify memory references in the original computer code. Memory references are classified as either regular memory references or irregular memory references. Regular memory references are controlled by a high locality cache mechanism. Original computer code is transformed, by a compiler, to generate transformed computer code in which the regular memory references are grouped into one or more memory reference streams, each memory reference stream having a leading memory reference, a trailing memory reference, and one or more middle memory references. Transforming of the original computer code comprises inserting, into the original computer code, instructions to execute initialization, lookup, and cleanup operations associated with the leading memory reference and trailing memory reference in a different manner from initialization, lookup, and cleanup operations for the one or more middle memory references.
摘要翻译：提供了针对高位置软件缓存的优化代码生成机制。解析原始计算机代码以识别原始计算机代码中的内存引用。内存引用被分类为常规内存引用或不规则内存引用。常规内存引用由高位置缓存机制控制。原始计算机代码由编译器转换以生成转换的计算机代码，其中常规存储器引用被分组成一个或多个存储器参考流，每个存储器参考流具有前导存储器引用，尾随存储器引用和一个或多个中间内存引用。原始计算机代码的转换包括将原始计算机代码中的指令以不同于初始化，查找和清除操作的方式与前导存储器引用和尾随存储器引用相关联的执行初始化，查找和清除操作的指令进行插入或更多的中间内存引用。

8. 发明申请

US20090249318A1 Data Transfer Optimized Software Cache for Irregular Memory References 有权
标题翻译：数据传输优化软件缓存用于不规则内存引用
公开(公告)号：US20090249318A1
公开(公告)日：2009-10-01
申请号：US12057456
申请日：2008-03-28
申请人： Eduard Ayguade , Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , Xavier Martorell , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
发明人： Eduard Ayguade , Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , Xavier Martorell , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/45 , G06F12/08
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for optimizing irregular memory references in computer code. These mechanisms may parse the computer code to identify memory references in the computer code. These mechanisms may further classify the memory references in the computer code as either regular memory references or irregular memory references. Moreover, the mechanisms may transform the computer code, by a compiler, to generate transformed computer code in which irregular memory references access a storage of a software cache of a data processing system through a transactional cache mechanism of the software cache.
摘要翻译：提供机制用于优化计算机代码中的不规则内存引用。这些机制可能解析计算机代码以识别计算机代码中的内存引用。这些机制可以将计算机代码中的存储器引用进一步分类为常规存储器引用或不规则存储器引用。此外，机制可以通过编译器转换计算机代码，以生成转换的计算机代码，其中不规则存储器引用通过软件高速缓存的事务高速缓存机制访问数据处理系统的软件高速缓存的存储。

9. 发明授权

US08561044B2 Optimized code generation targeting a high locality software cache 失效
标题翻译：针对高位置软件缓存的优化代码生成
公开(公告)号：US08561044B2
公开(公告)日：2013-10-15
申请号：US12246602
申请日：2008-10-07
申请人： Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
发明人： Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4442
摘要： Mechanisms for optimized code generation targeting a high locality software cache are provided. Original computer code is parsed to identify memory references in the original computer code. Memory references are classified as either regular memory references or irregular memory references. Regular memory references are controlled by a high locality cache mechanism. Original computer code is transformed, by a compiler, to generate transformed computer code in which the regular memory references are grouped into one or more memory reference streams, each memory reference stream having a leading memory reference, a trailing memory reference, and one or more middle memory references. Transforming of the original computer code comprises inserting, into the original computer code, instructions to execute initialization, lookup, and cleanup operations associated with the leading memory reference and trailing memory reference in a different manner from initialization, lookup, and cleanup operations for the one or more middle memory references.
摘要翻译：提供了针对高位置软件缓存的优化代码生成机制。解析原始计算机代码以识别原始计算机代码中的内存引用。内存引用被分类为常规内存引用或不规则内存引用。常规内存引用由高位置缓存机制控制。原始计算机代码由编译器转换以生成转换的计算机代码，其中常规存储器引用被分组成一个或多个存储器参考流，每个存储器参考流具有前导存储器引用，尾随存储器引用和一个或多个中间内存引用。原始计算机代码的转换包括将原始计算机代码中的指令以不同于初始化，查找和清除操作的方式与前导存储器引用和尾随存储器引用相关联的执行初始化，查找和清除操作的指令进行插入或更多的中间内存引用。

10. 发明授权

US08561043B2 Data transfer optimized software cache for irregular memory references 有权
标题翻译：数据传输优化的软件缓存用于不规则内存引用
公开(公告)号：US08561043B2
公开(公告)日：2013-10-15
申请号：US12057456
申请日：2008-03-28
申请人： Eduard Ayguade , Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , Xavier Martorell , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
发明人： Eduard Ayguade , Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , Xavier Martorell , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
IPC分类号： G06F9/45 , G06F12/08
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for optimizing irregular memory references in computer code. These mechanisms may parse the computer code to identify memory references in the computer code. These mechanisms may further classify the memory references in the computer code as either regular memory references or irregular memory references. Moreover, the mechanisms may transform the computer code, by a compiler, to generate transformed computer code in which irregular memory references access a storage of a software cache of a data processing system through a transactional cache mechanism of the software cache.
摘要翻译：提供机制用于优化计算机代码中的不规则内存引用。这些机制可能解析计算机代码以识别计算机代码中的内存引用。这些机制可以将计算机代码中的存储器引用进一步分类为常规存储器引用或不规则存储器引用。此外，机制可以通过编译器转换计算机代码，以生成转换的计算机代码，其中不规则存储器引用通过软件高速缓存的事务高速缓存机制访问数据处理系统的软件高速缓存的存储。

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