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1. 发明申请

US20070096332A1 Electronic component, module, module assembling method, module identification method and module environment setting method 审中-公开
标题翻译：电子元件，模块，模块组装方法，模块识别方法和模块环境设置方法
公开(公告)号：US20070096332A1
公开(公告)日：2007-05-03
申请号：US10558269
申请日：2004-05-28
申请人： Tomotoshi Satoh , Yoshihiko Nemoto , Kenji Takahashi , Yukiharu Akiyama
发明人： Tomotoshi Satoh , Yoshihiko Nemoto , Kenji Takahashi , Yukiharu Akiyama
IPC分类号： H01L23/52
CPC分类号： H01L24/06 , H01L23/481 , H01L25/0657 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06593 , H01L2924/01004 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01055 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011
摘要： An electronic component capable of being assembled into a module in the form of a stack of a plurality of layers is provided. Terminals of terminal groups (31 to 36) are formed so as to have rotational symmetry of a predetermined fold-number or have rotational symmetry and symmetry with respect to the plane containing a symmetric axis line. The terminals (A0 to A7, RFCG) of common connection terminal groups (32, 36) have connecting portions formed on the both surfaces in a stacking direction. Among the terminals of individual connection terminal groups (31, 33), a specific terminal CS; KEY has a connection portion formed at least on one of the both surfaces in the stacking direction while the remaining associated terminals NC; DMY have connection portions formed on the both surfaces in the stacking direction. When such electronic components (20) are stacked so as to be shifted from each other by the angle obtained by dividing 360 degrees by the predetermined fold-number or in addition in the inverted state, it is possible to assemble a module using the electronic components (20) having the same configuration.
摘要翻译：提供能够组装成多层叠层形式的模块的电子部件。端子组（31〜36）的端子形成为具有预定折叠数的旋转对称，或者相对于包含对称轴线的平面具有旋转对称性和对称性。公共连接端子组（32,36）的端子（A 0〜A 7，RFCG）具有在层叠方向上形成在两面的连接部。在各个连接端子组（31,33）的端子中，具体端子CS; KEY具有在层叠方向上形成在两个表面中的至少一个上的连接部分，而剩余的关联端子NC; DMY在层叠方向的两面形成有连接部。当这样的电子部件（20）被堆叠以便以360度除以预定的折叠数，或者在倒置状态下相互偏移所获得的角度时，可以使用电子部件（20）具有相同的构造。

2. 发明申请

US20060056247A1 Memory device 失效
标题翻译：内存设备
公开(公告)号：US20060056247A1
公开(公告)日：2006-03-16
申请号：US11227038
申请日：2005-09-14
申请人： Tomotoshi Satoh
发明人： Tomotoshi Satoh
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C5/02 , G11C5/04 , G11C29/785
摘要： First memory chips each have a memory cell as storage means for storing data and do not have a redundant memory cell as redundant storage means for repairing an erroneous bit in the memory cell. Furthermore, a logic minimal in degree is solely provided for operation on a control logic of a second memory chip. The second memory chip has a control logic for effecting memory control of the memory cells, the redundant memory cells, etc. and a redundant memory cell for repairing an error bit of the first memory chips. The memory device is structured by stacking the first and second memory chips.
摘要翻译：第一存储器芯片各自具有作为用于存储数据的存储装置的存储单元，并且没有冗余存储单元作为用于修复存储器单元中的错误位的冗余存储装置。此外，仅对第二存储器芯片的控制逻辑进行操作的逻辑最小程度。第二存储器芯片具有用于实现存储器单元，冗余存储器单元等的存储器控制的控制逻辑和用于修复第一存储器芯片的错误位的冗余存储单元。存储器件通过堆叠第一和第二存储器芯片来构造。

3. 发明申请

US20100313930A1 SOLAR BATTERY MODULE, AND ELECTRONIC COMPONENT, ELECTRIC COMPONENT AND ELECTRONIC APPARATUS MOUNTING THE SAME 审中-公开
标题翻译：太阳能电池组件和电子元件，电气元件和电子设备安装
公开(公告)号：US20100313930A1
公开(公告)日：2010-12-16
申请号：US12792204
申请日：2010-06-02
申请人： Masato Yokobayashi , Tomotoshi Satoh , Hiroyuki Nakanishi
发明人： Masato Yokobayashi , Tomotoshi Satoh , Hiroyuki Nakanishi
IPC分类号： H01L31/042
CPC分类号： H04M19/08 , H01L31/0504 , Y02E10/50
摘要： All solar battery cells are in a matrix disposition. Each row of the matrix includes at least two cell groups, and each column of the matrix includes at least two cell groups.
摘要翻译：所有太阳能电池单元都是矩阵配置。矩阵的每行包括至少两个单元组，矩阵的每列包括至少两个单元组。

4. 发明申请

US20100294358A1 SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：半导体封装
公开(公告)号：US20100294358A1
公开(公告)日：2010-11-25
申请号：US12783283
申请日：2010-05-19
申请人： Hiroyuki NAKANISHI , Masahiro Okita , Kohji Miyata , Tomotoshi Satoh , Etsuko Ishizuka , Masato Yokobayashi
发明人： Hiroyuki NAKANISHI , Masahiro Okita , Kohji Miyata , Tomotoshi Satoh , Etsuko Ishizuka , Masato Yokobayashi
IPC分类号： H01L23/488 , H01L31/02
CPC分类号： H01L24/83 , H01L23/49816 , H01L24/29 , H01L24/32 , H01L31/0201 , H01L31/048 , H01L31/0508 , H01L31/0512 , H01L2224/29011 , H01L2224/29101 , H01L2224/2919 , H01L2224/29339 , H01L2224/32057 , H01L2224/83194 , H01L2224/83385 , H01L2224/838 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/351 , Y02E10/50 , H01L2924/00 , H01L2924/3512 , H01L2224/8384
摘要： A semiconductor chip and an interposer are bonded by a conductive die bonding material. Between the semiconductor chip and the interposer, an application region in which the die bonding material resides and a region in which a sealing resin resides are provided. This allows adhesivity between the semiconductor chip and the interposer to be higher than that in conventional semiconductor packages, thereby causing no detachment at the adhesive interface. As a result, it becomes possible to improve electrical property and long-term reliability as compared to conventional semiconductor packages. Moreover, it is also possible to prevent the semiconductor chip from warping.
摘要翻译：半导体芯片和内插器通过导电芯片接合材料接合。在半导体芯片和插入件之间设置有芯片接合材料所在的应用区域和密封树脂所在的区域。这使得半导体芯片和插入件之间的粘合性比常规半导体封装中的粘合性高，从而在粘合剂界面处不发生分离。结果，与以往的半导体封装相比，能够提高电气特性和长期可靠性。此外，还可以防止半导体芯片翘曲。

5. 发明授权

US07218559B2 Memory device having redundant memory for repairing defects 失效
标题翻译：具有用于修复缺陷的冗余存储器的存储器件
公开(公告)号：US07218559B2
公开(公告)日：2007-05-15
申请号：US11227038
申请日：2005-09-14
申请人： Tomotoshi Satoh
发明人： Tomotoshi Satoh
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C5/02 , G11C5/04 , G11C29/785
摘要： First memory chips each have a memory cell as storage means for storing data and do not have a redundant memory cell as redundant storage means for repairing an erroneous bit in the memory cell. Furthermore, a logic minimal in degree is solely provided for operation on a control logic of a second memory chip. The second memory chip has a control logic for effecting memory control of the memory cells, the redundant memory cells, etc. and a redundant memory cell for repairing an error bit of the first memory chips. The memory device is structured by stacking the first and second memory chips.
摘要翻译：第一存储器芯片各自具有作为用于存储数据的存储装置的存储单元，并且没有冗余存储单元作为用于修复存储器单元中的错误位的冗余存储装置。此外，仅对第二存储器芯片的控制逻辑进行操作的逻辑最小程度。第二存储器芯片具有用于实现存储器单元，冗余存储器单元等的存储器控制的控制逻辑和用于修复第一存储器芯片的错误位的冗余存储单元。存储器件通过堆叠第一和第二存储器芯片来构造。

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