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1. 发明申请

US20080239063A1 STEREOSCOPIC OBSERVATION SYSTEM 有权
标题翻译：立体观察系统
公开(公告)号：US20080239063A1
公开(公告)日：2008-10-02
申请号：US12055027
申请日：2008-03-25
申请人： Tomonori ISHIKAWA , Kazuo MORITA , Masahiro KUDO , Junichi NOZAWA , Kazuo BANJU
发明人： Tomonori ISHIKAWA , Kazuo MORITA , Masahiro KUDO , Junichi NOZAWA , Kazuo BANJU
IPC分类号： H04N13/02
CPC分类号： G02B23/2415 , H04N13/239 , H04N13/344 , H04N13/398
摘要： A stereoscopic observation system includes a stereoscopic image pick up apparatus to pick up left and right images at an inward angle, a stereoscopic image display apparatus to transmit the left and right images picked up by the stereoscopic image pick up apparatus to an observer so that the images are stereoscopically observed at a convergence angle, a convergence angle change portion provided in the stereoscopic image display apparatus and to change the convergence angle, a recognition portion to recognize the stereoscopic image pick up apparatus, and a control portion to control the convergence angle change portion on the basis of the result of the recognition in the recognition portion so that the convergence angle is substantially equal to the inward angle.
摘要翻译：立体观察系统包括立体图像拾取装置，用于以向内的角度拾取左和右图像;立体图像显示装置，用于将由立体图像拾取装置拾取的左和右图像发送给观察者，使得收敛角度立体观察图像，立体图像显示装置中设置的会聚角变化部，变更会聚角，识别部，识别立体图像拾取装置，控制部，控制会聚角变化基于识别部分中的识别结果，使得会聚角度基本上等于向内的角度。

2. 发明申请

US20080297392A1 SIGNAL PROCESSING METHOD AND DEVICE, AND ANALOG/DIGITAL CONVERTING DEVICE 有权
标题翻译：信号处理方法和装置，以及模拟/数字转换装置
公开(公告)号：US20080297392A1
公开(公告)日：2008-12-04
申请号：US12187773
申请日：2008-08-07
申请人： Masahiro KUDO , Hiroshi Yamazaki
发明人： Masahiro KUDO , Hiroshi Yamazaki
IPC分类号： H03M1/12
CPC分类号： H03M1/504
摘要： The first and second time-domain signals are received, and a difference between the pulse width of the first time-domain signal and the pulse width of the second time-domain signal within a unit time for carrying one item of analog signal information is obtained. The obtained difference is treated as positive information if the pulse width of the first time-domain signal is greater than the pulse width of the second time-domain signal, or as negative information if the pulse width of the first time-domain signal is smaller than the pulse width of the second time-domain signal.
摘要翻译：接收第一和第二时域信号，并且获得用于携带一个模拟信号信息的单位时间内的第一时域信号的脉冲宽度与第二时域信号的脉冲宽度之间的差。如果第一时域信号的脉冲宽度大于第二时域信号的脉冲宽度，则获得的差值被视为正信息，或者如果第一时域信号的脉冲宽度较小，则将其作为负信息比第二时域信号的脉冲宽度。

3. 发明申请

US20100039178A1 AMPLIFIER CIRCUIT 有权
标题翻译：放大器电路
公开(公告)号：US20100039178A1
公开(公告)日：2010-02-18
申请号：US12567492
申请日：2009-09-25
申请人： Tomoyuki ARAI , Masahiro KUDO , Shinji YAMAURA
发明人： Tomoyuki ARAI , Masahiro KUDO , Shinji YAMAURA
IPC分类号： H03F3/45 , H03F3/16
CPC分类号： H03F3/45183 , H03F1/3211 , H03F3/45188 , H03F2200/456 , H03F2203/45302 , H03F2203/45466 , H03F2203/45638
摘要： An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor.
摘要翻译：放大器电路包括作为实现上述目的的装置的放大器单元和电流控制电路。放大器单元包括补偿输出特性增益的增益补偿MOS晶体管和补偿输出特性的线性度的线性补偿MOS晶体管。增益补偿MOS晶体管的源极连接到线性补偿MOS晶体管的漏极。输入信号被施加到线性补偿MOS晶体管的栅极。增益补偿MOS晶体管的漏极被设置为输出。电流控制电路进行控制，以便在增益补偿MOS晶体管的漏极和源极之间通过预定电流，并且在线性补偿MOS晶体管的漏极和源极之间通过预定电流。

4. 发明申请

US20080201396A1 Signal processing apparatus and the correcting method 有权
标题翻译：信号处理装置和校正方法
公开(公告)号：US20080201396A1
公开(公告)日：2008-08-21
申请号：US12010985
申请日：2008-01-31
申请人： Masahiro KUDO
发明人： Masahiro KUDO
IPC分类号： G06F17/10
CPC分类号： H04L25/061 , H03H11/1252 , H03H11/1291 , H03H2011/0494
摘要： A signal processing apparatus, comprising: a first filter on an in-phase signal channel; a second filter on a quadrature signal channel; a plurality of filter stages having each of more than one signal paths crossing each other which connects the first filter and the second filter; and at least more than one of the filter stages of more than one of a plurality of the filter stages comprises a switching circuit disconnecting more than one of the signal paths and a correction unit correcting direct current offsets of the first filter and the second filter by using the switching circuit.
摘要翻译：一种信号处理装置，包括：同相信号通道上的第一滤波器; 在正交信号信道上的第二滤波器; 多个滤波器级，其具有彼此交叉的多于一个的信号路径中的每一个，其连接所述第一滤波器和所述第二滤波器; 并且多个滤波器级中的多于一个的滤波器级中的至少一个以上的滤波器级包括切换多个信号路径的切换电路和校正单元，该校正单元通过以下步骤校正第一滤波器和第二滤波器的直流偏移：使用开关电路。

5. 发明申请

US20090184752A1 BIAS CIRCUIT 审中-公开
标题翻译：偏置电路
公开(公告)号：US20090184752A1
公开(公告)日：2009-07-23
申请号：US12411104
申请日：2009-03-25
申请人： Masahiro KUDO
发明人： Masahiro KUDO
IPC分类号： G05F1/10
CPC分类号： G05F3/30 , G05F3/26
摘要： A bias circuit includes a first and a second transistors to which a common gate voltage is supplied, a load circuit coupled to drains of the first and the second transistors, a control circuit generating a control signal based on a signal from the load circuit, a current source controlled based on the control signal and coupled to the first and the second transistors, and a first impedance circuit coupled between the second transistor and the current source.
摘要翻译：偏置电路包括供给公共栅极电压的第一和第二晶体管，耦合到第一和第二晶体管的漏极的负载电路，基于来自负载电路的信号产生控制信号的控制电路，基于控制信号控制并耦合到第一和第二晶体管的电流源以及耦合在第二晶体管和电流源之间的第一阻抗电路。

6. 发明申请

US20100283527A1 Analog Switch 审中-公开
标题翻译：模拟开关
公开(公告)号：US20100283527A1
公开(公告)日：2010-11-11
申请号：US12839939
申请日：2010-07-20
申请人： Kazuaki OISHI , Masahiro KUDO
发明人： Kazuaki OISHI , Masahiro KUDO
IPC分类号： H03K17/16
CPC分类号： H03K17/693 , H03F3/45475 , H03F2203/45138 , H03F2203/45528 , H03F2203/45591 , H03F2203/45616 , H03K17/161 , H03K17/6871 , H03K2217/0036
摘要： An analog switch comprises a first transistor, a second transistor, the drain and the source thereof being connected between said first input terminal and a second output terminal whereto said second signal is output and the gate thereof being grounded or connected to a supply voltage node, a third transistor, the drain and the source thereof being connected between a second input terminal whereto said second signal is input and said second output terminal and said third transistor being turned on and off by a control signal provided to the gate thereof; and a fourth transistor, the drain and the source thereof being connected between said second input terminal and said first output terminal and the gate thereof being grounded or connected to a supply voltage node.
摘要翻译：模拟开关包括第一晶体管，第二晶体管，漏极和源极连接在所述第一输入端和输出所述第二信号的第二输出端之间，其栅极接地或连接到电源电压节点，第三晶体管，其漏极和源极连接在输入所述第二信号的第二输入端子和所述第二输出端子和所述第三晶体管之间通过提供给其栅极的控制信号导通和截止; 以及第四晶体管，其漏极和源极连接在所述第二输入端子和所述第一输出端子之间，其栅极接地或连接到电源电压节点。

7. 发明申请

US20080191680A1 BIAS CIRCUIT 有权
标题翻译：偏置电路
公开(公告)号：US20080191680A1
公开(公告)日：2008-08-14
申请号：US12058401
申请日：2008-03-28
申请人： Masahiro KUDO
发明人： Masahiro KUDO
IPC分类号： G05F3/28
CPC分类号： G05F3/262
摘要： A control circuit U1 comprises four PMOS transistors MP1-MP4 and receives a voltage Vn and a voltage Vss. MP1 and MP3, and, MP2 and MP4 are respectively connected in series between power supply Vdd and a fixed voltage Vss. Gate terminal of MP2 is connected to Vss. Reference current and its copy current F1 respectively flow through NMOS transistors M1 and M2, of which respective source terminals are connected to Vss. Gate width of M2 is a quarter of that of M1. Drain terminal is connected to the gate terminals of MP1 and MP2. Node between source terminal of MP2 and drain terminal of MP3 is connected to gate terminal of MP1, and node between source terminal of MP2 and drain terminal of MP4 is connected to gate terminal of MP2. The control circuit U1 controls gate terminal voltage of M1 to make an overdrive voltage of M1 becomes Vn.
摘要翻译：控制电路U 1包括四个PMOS晶体管MP 1 -MP 4，并且接收电压Vn和电压Vss。 MP 1和MP 3以及MP 2和MP 4分别串联在电源Vdd和固定电压Vss之间。 MP 2的栅极端子连接到Vss。参考电流及其复制电流F 1分别流过其中各个源极端子连接到Vss的NMOS晶体管M 1和M 2。 M 2的栅极宽度是M 1的栅极宽度的四分之一。漏极端子连接到MP 1和MP 2的栅极端子。 MP2的源极端子和MP3的漏极端子之间的节点连接到MP 1的栅极端子，MP2的源极端子和MP4的漏极端子之间的节点连接到MP 2的栅极端子。控制电路U 1控制M 1的栅极端子电压，使得M1的过驱动电压变为Vn。

8. 发明申请

US20100033249A1 DIFFERENTIAL AMPLIFIER 审中-公开
标题翻译：差分放大器
公开(公告)号：US20100033249A1
公开(公告)日：2010-02-11
申请号：US12537332
申请日：2009-08-07
申请人： Masahiro KUDO
发明人： Masahiro KUDO
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/193 , H03F2200/366 , H03F2200/411 , H03F2203/45352 , H03F2203/45364 , H03F2203/45512 , H03F2203/45668 , H03F2203/45702 , H03F2203/45722
摘要： A differential amplifier includes first and second transistors having source terminals coupled to each other at a first common node, a first common current source coupled to the first common node, and an in-phase signal input terminal configured to input, to the first common node, an in-phase signal of first and second input signals inputted to gate terminals of the first and second transistors.
摘要翻译：差分放大器包括具有在第一公共节点处彼此耦合的源极端子的第一和第二晶体管，耦合到第一公共节点的第一公共电流源和被配置为输入到第一公共节点的同相信号输入端子，输入到第一和第二晶体管的栅极端的第一和第二输入信号的同相信号。

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