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    • 3. 发明授权
    • Display device
    • 显示设备
    • US07180246B2
    • 2007-02-20
    • US10931120
    • 2004-09-01
    • Tomoki NakamuraYoshiyuki KanekoToshifumi Ozaki
    • Tomoki NakamuraYoshiyuki KanekoToshifumi Ozaki
    • G09G3/10
    • H01J29/085G09G3/22G09G2320/04G09G2320/043H01J31/127
    • To detect a dark current when an abnormal discharge occurs between an anode and respective electrodes, on an inner surface of a front substrate, a dark current detection electrode is formed in a state that the dark current detection electrode is positioned adjacent to the outside of a screen display region on which an anode is formed and on a plane substantially equal to a plane on which the anode is formed. Then, between an electrode terminal of the dark current detection electrode and a ground, an ammeter which detects the flow of a dark current and a DC power source having a preset voltage value which is more or less lower than a high voltage supplied to the anode are connected in series.
    • 为了在阳极和各个电极之间发生异常放电时检测暗电流,在前基板的内表面上,在暗电流检测电极位于邻近于正电极的外部的状态下形成暗电流检测电极 在其上形成有阳极的屏幕显示区域和基本上等于形成有阳极的平面的平面上。 然后,在暗电流检测电极的电极端子与地之间,检测暗电流的电流的电流表以及具有比供给阳极的高电压低的电压值的直流电源 串联连接。
    • 7. 发明申请
    • Image Display Device
    • 图像显示设备
    • US20090033589A1
    • 2009-02-05
    • US12127851
    • 2008-05-28
    • Toshifumi Ozaki
    • Toshifumi Ozaki
    • G09G3/20
    • G09G3/3688G09G3/22G09G2310/027
    • An increase in the circuit size of a drive circuit that accompanies multi-gradation is reduced. Herein, VI0 to VIM are modulation circuit reference voltages in which a prescribed range, i.e., from a non-emission voltage VEOFF to a maximum emission voltage VEON, is divided in M equal parts. Higher-order dividing resistor (40) equally divides the parts of the modulation circuit reference voltages VI0 to VIM (where VI0>VI1 . . . >VIM−1>VIM) and generates 2J+1 higher-order gradation voltages v0 to v8M (where 8M is equal to 2J) A higher-order decoder unit (41) selects two adjacent voltages from the higher-order gradation voltages in accordance with the data of the higher-order J bits held in the data latch. Complimentary MOSFET selection switches (47-1) and (47-2) open and close in accordance with the lowest-order bit data inputted to the higher-order decoder unit (41). A lower-order dividing resistor (43) equally divides the voltage between the selected high-voltage higher-order gradation voltage vl and the low-voltage higher-order gradation voltage v1+1, and generates 2K gradation voltages vl0 to vln−1 (where n is equal to 2K). A lower-order decoder unit (44) selectively outputs an output voltage from the gradation voltages generated by the dividing resistors in accordance with the data of the lower-order K bits held in the data latch.
    • 伴随多层次的驱动电路的电路尺寸的增加减小。 这里,VI0至VIM是其规定范围即从非发射电压VEOFF到最大发射电压VEON的规定范围的M等分的调制电路参考电压。 高阶分频电阻器(40)将调制电路参考电压VI0至VIM的部分(其中VI0> VI1 ... VIM-1> VIM)等分,并产生2J + 1高阶灰度电压v0至v8M( 其中8M等于2J)高阶解码器单元(41)根据保存在数据锁存器中的高阶J位的数据从高阶灰度电压中选择两个相邻的电压。 免费MOSFET选择开关(47-1)和(47-2)根据输入到高阶解码器单元(41)的最低位数据进行打开和关闭。 低阶分压电阻(43)将所选择的高电压高阶灰度电压v1和低电压高阶灰度电压v1 + 1之间的电压等分,并产生2K灰度电压v10至vln-1( 其中n等于2K)。 低阶解码器单元(44)根据保存在数据锁存器中的低位K位的数据选择性地输出由分压电阻产生的灰度电压的输出电压。
    • 9. 发明申请
    • Display device
    • 显示设备
    • US20060187151A1
    • 2006-08-24
    • US11301936
    • 2005-12-13
    • Yoshihisa OoishiToshifumi OzakiFumio HarunaToshimitsu WatanabeYoshiro Mikami
    • Yoshihisa OoishiToshifumi OzakiFumio HarunaToshimitsu WatanabeYoshiro Mikami
    • G09G3/20
    • G09G3/22G09G2310/0221G09G2310/0267G09G2310/027G09G2320/0223
    • Input display data (D0, D1, D2) are converted into currents ij which are allowed to flow into respective pixels by a data/current conversion part 66, electric currents IN at end portions of a row wiring are calculated by a current IN calculation circuit 68-2 using the currents ij, and a voltage drop VN at an end portion of the row wiring is calculated by a voltage drop VN calculation circuit 68-4 using the current IN. On the other hand, the sum of the currents ij is calculated by a current ij calculation circuit 68-6, and a current Im−1 which flows between the pixels is calculated by a current Im−1 calculation circuit 68-7 using the sum of the currents ij and the currents IN. Next, using a currents Ij between the respective pixels and the voltage drops VN calculated by a current Ij calculation circuit 68-8, a voltage drop Vm−1 is calculated by a voltage drop Vm−1 calculation circuit 68-9, and the voltage drop Vm−1 is converted into the data by the voltage/data conversion part 67, and the data and the input display data are added to each other in an adding circuit 64 so as to obtain the output display data (D0, D1, D2) which are corrected by an amount corresponding to the voltage drop.
    • 输入显示数据(D 0,D 1,D 2)被转换成数据/电流转换部66被允许流入各个像素的电流ij,行布线的端部的电流IN由电流 通过使用电流IN的电压降VN计算电路68-4计算使用电流ij的IN计算电路68-2和行布线的端部处的电压降VN。 另一方面,通过电流ij计算电路68-6计算电流ij的和,并且通过电流Im-1计算电路68-7使用总和计算在像素之间流动的电流Im-1 的电流ij和电流IN。 接下来,使用各个像素之间的电流Ij和由电流Ij计算电路68-8计算的电压降VN,通过电压降Vm-1计算电路68-9计算电压降Vm-1,并且电压 通过电压/数据转换部分67将Vm-1转换成数据,并且在加法电路64中将数据和输入显示数据相加,以获得输出显示数据(D 0,D 1 ,D 2),其被对应于电压降的量校正。