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1. 发明申请

US20060169673A1 Plasma processing method and apparatus 失效
公开(公告)号：US20060169673A1
公开(公告)日：2006-08-03
申请号：US11397626
申请日：2006-04-05
申请人： Tomohiro Okumura , Yukihiro Maegawa , Hiroyuki Suzuki , Ichiro Nakayama
发明人： Tomohiro Okumura , Yukihiro Maegawa , Hiroyuki Suzuki , Ichiro Nakayama
IPC分类号： C23F1/00
CPC分类号： H01J37/32082 , C23F4/00 , Y02E50/30
摘要： A plasma processing apparatus includes a vacuum vessel, a substrate electrode for supporting a substrate, and an antenna disposed in opposition to the substrate electrode and covered with an insulating antenna cover. A first high-frequency power supplies a high-frequency power of a 30 MHz to 3 GHz frequency to the antenna, and a second high-frequency power supply supplies a high-frequency power of a 100 kHz to 20 MHz. A refrigerant supply unit is provided for supplying a refrigerant flow to the antenna, and an electrically conductive sheet is provided between the antenna and the antenna cover. The electrically conductive sheet has a surface that is parallel to the substrate electrode and is larger than an opposing surface of the antenna.

2. 发明授权

US06707253B2 Matching circuit and plasma processing apparatus 有权
标题翻译：匹配电路和等离子体处理装置
公开(公告)号：US06707253B2
公开(公告)日：2004-03-16
申请号：US10324031
申请日：2002-12-20
申请人： Kenji Sumida , Tomohiro Okumura , Yukihiro Maegawa , Ichiro Nakayama , Kibatsu Shinohara , Minoru Kanda , Shiniti Matamura
发明人： Kenji Sumida , Tomohiro Okumura , Yukihiro Maegawa , Ichiro Nakayama , Kibatsu Shinohara , Minoru Kanda , Shiniti Matamura
IPC分类号： H01J2336
CPC分类号： H01J37/32082 , H01J37/32183
摘要： The present invention provides a matching circuit which has a wide range in which matching can be achieved and the matched state of which is stabilized with respect to a change in the load state. To an input terminal (31) of a matching circuit (30), one terminal of a first variable reactance element (32) is connected. The other terminal of the first variable reactance element (32) is connected to a point between a first fixed reactance element (33a) and a second fixed reactance element (33b), which are connected in series. The first fixed reactance element (33a) is grounded, and the second fixed reactance element (33b) is connected to one terminal of a second variable reactance element (36) and connected to one terminal of a stripline (37). The other terminal of the second variable reactance element (36) is grounded, and the other terminal of the stripline (37) is connected to an output terminal (38).
摘要翻译：本发明提供一种匹配电路，其具有可以实现匹配的宽范围，并且其匹配状态相对于负载状态的变化是稳定的。对于匹配电路（30）的输入端子（31），连接第一可变电抗元件（32）的一个端子。第一可变电抗元件（32）的另一个端子连接到串联连接的第一固定电抗元件（33a）和第二固定电抗元件（33b）之间的点。第一固定电抗元件（33a）接地，第二固定电抗元件（33b）连接到第二可变电抗元件（36）的一个端子，并连接到带状线（37）的一个端子。第二可变电抗元件（36）的另一个端子接地，并且带状线（37）的另一个端子连接到输出端子（38）。

3. 发明授权

US06864640B2 Plasma processing method and apparatus thereof 失效
标题翻译：等离子体处理方法及其装置
公开(公告)号：US06864640B2
公开(公告)日：2005-03-08
申请号：US09918823
申请日：2001-08-01
申请人： Tomohiro Okumura , Yukihiro Maegawa , Izuru Matsuda
发明人： Tomohiro Okumura , Yukihiro Maegawa , Izuru Matsuda
IPC分类号： B81C1/00 , C23F4/00 , H01J37/32 , H01L21/205 , H01L21/302 , H01L21/3065 , G09G3/10
CPC分类号： H01J37/3244
摘要： A plasma processing method includes introducing a gas into a vacuum chamber through a hole of a dielectric tube attached to a metal body fixed to the vacuum chamber while exhausting from the vacuum chamber to keep the vacuum chamber within a specified pressure. High-frequency power with a frequency ranging from 100 kHz to 3 GHz is applied to a plasma source provided so as to face a substrate mounted on a substrate electrode in the vacuum chamber to generate plasma in the vacuum chamber to perform plasma processing of the substrate.
摘要翻译：等离子体处理方法包括：通过安装在固定于真空室的金属体的电介质管的孔内将气体引入真空室，同时从真空室排出，将真空室保持在规定的压力范围内。施加频率范围从100kHz至3GHz的高频功率施加到等离子体源，所述等离子体源设置为面对安装在真空室中的基板电极上的基板，以在真空室中产生等离子体，以执行基板的等离子体处理。

4. 发明授权

US06830653B2 Plasma processing method and apparatus 失效
标题翻译：等离子体处理方法和装置
公开(公告)号：US06830653B2
公开(公告)日：2004-12-14
申请号：US10207183
申请日：2002-07-30
申请人： Tomohiro Okumura , Yukihiro Maegawa , Izuru Matsuda , Takayuki Kai , Mitsuo Saitoh
发明人： Tomohiro Okumura , Yukihiro Maegawa , Izuru Matsuda , Takayuki Kai , Mitsuo Saitoh
IPC分类号： C23C1600
CPC分类号： H01J37/32091 , C23C16/4412 , H01J37/32192 , H01J37/3222 , H01J37/3244 , H01J37/32834
摘要： A plasma processing method for generating plasma in a vacuum chamber and processing a substrate placed on a substrate electrode, the plasma being generated by supplying a high-frequency power having a frequency of 50 MHz to 3 GHz to an antenna provided opposite to the substrate electrode while interior of the vacuum chamber is controlled to a specified pressure by supplying a gas into the vacuum chamber and exhausting the interior of the vacuum chamber, the method includes with a dielectric plate being sandwiched between the antenna and the vacuum chamber and both the antenna and the dielectric plate projecting into the vacuum chamber, controlling plasma distribution on the substrate with an annular and recessed slit provided between the antenna and the vacuum chamber, and processing the substrate in a state where the antenna cover is fixed by making both an inner side face of the slit and the antenna covered with an antenna cover, making a bottom face of the slit covered with a slit cover, supporting the antenna cover by the slit cover, and fixing the slit cover to a wall surface of the vacuum chamber.
摘要翻译：一种用于在真空室中产生等离子体并处理放置在基板电极上的基板的等离子体处理方法，所述等离子体是通过将频率为50MHz至3GHz的高频电源提供给与基板电极相对设置的天线而产生的通过向真空室供给气体并排出真空室的内部，真空室的内部被控制到规定的压力，该方法包括夹在天线和真空室之间的电介质板，天线和电介质板突出到真空室中，通过设置在天线和真空室之间的环形和凹槽来控制基板上的等离子体分布，并且通过使天线盖固定的状态来处理基板的狭缝和天线覆盖有天线盖，使狭缝的底面覆盖有狭缝c 通过狭缝盖支撑天线罩，并将狭缝盖固定到真空室的壁面。

5. 发明授权

US07406925B2 Plasma processing method and apparatus 失效
标题翻译：等离子体处理方法和装置
公开(公告)号：US07406925B2
公开(公告)日：2008-08-05
申请号：US10983670
申请日：2004-11-09
申请人： Tomohiro Okumura , Yukihiro Maegawa , Izuru Matsuda , Takayuki Kai , Mitsuo Saitoh
发明人： Tomohiro Okumura , Yukihiro Maegawa , Izuru Matsuda , Takayuki Kai , Mitsuo Saitoh
IPC分类号： H01L21/00 , C23C16/00
CPC分类号： H01J37/32091 , C23C16/4412 , H01J37/32192 , H01J37/3222 , H01J37/3244 , H01J37/32834
摘要： A plasma processing apparatus including a vacuum chamber, a gas supply unit for supplying gas into the vacuum chamber, an exhausting unit for exhausting the interior of the vacuum chamber, a pressure-regulating valve for controlling the interior of the vacuum chamber to a specified pressure, a substrate electrode for placing thereon a substrate within the vacuum chamber, an antenna provided opposite to the substrate electrode, and a high-frequency power supply capable of supplying to the antenna a high-frequency power having a frequency of 50 MHz to 3 GHz. The plasma processing apparatus also has a dielectric plate sandwiched between the antenna and an inner surface of the vacuum chamber, an antenna cover for covering side surfaces of the antenna and the dielectric plate and a substrate-facing surface of the antenna, a slit cover for covering an exposed surface of the substrate-facing inner surface of the vacuum chamber and fixing the antenna cover to a wall surface of the vacuum chamber. Also, a heat-conducting sheet is provided between the antenna and the antenna cover.
摘要翻译：一种等离子体处理装置，包括真空室，用于向真空室供应气体的气体供应单元，用于排出真空室内部的排气单元，用于将真空室内部控制到特定压力的压力调节阀，用于将真空室内的基板放置的基板电极，与基板电极相对设置的天线，以及能够向天线供给频率为50MHz〜3GHz的高频电力的高频电源。等离子体处理装置还具有夹在天线和真空室的内表面之间的电介质板，用于覆盖天线和电介质板的侧表面的天线盖和天线的面向基板的表面，狭缝盖覆盖真空室的面向基板的内表面的暴露表面，并将天线盖固定到真空室的壁表面。此外，在天线和天线罩之间设置导热片。

6. 发明申请

US20050082005A1 Plasma processing method and apparatus 失效
标题翻译：等离子体处理方法和装置
公开(公告)号：US20050082005A1
公开(公告)日：2005-04-21
申请号：US10983670
申请日：2004-11-09
申请人： Tomohiro Okumura , Yukihiro Maegawa , Izuru Matsuda , Takayuki Kai , Mitsuo Saitoh
发明人： Tomohiro Okumura , Yukihiro Maegawa , Izuru Matsuda , Takayuki Kai , Mitsuo Saitoh
IPC分类号： C23C16/00 , C23F1/00 , H01J37/32 , H01L21/00 , H05H1/24
CPC分类号： H01J37/32091 , C23C16/4412 , H01J37/32192 , H01J37/3222 , H01J37/3244 , H01J37/32834
摘要： A plasma processing method for generating plasma in a vacuum chamber and processing a substrate placed on a substrate electrode, the plasma being generated by supplying a high-frequency power having a frequency of 50 MHz to 3 GHz to an antenna provided opposite to the substrate electrode while interior of the vacuum chamber is controlled to a specified pressure by supplying a gas into the vacuum chamber and exhausting the interior of the vacuum chamber, the method includes with a dielectric plate being sandwiched between the antenna and the vacuum chamber and both the antenna and the dielectric plate projecting into the vacuum chamber, controlling plasma distribution on the substrate with an annular and recessed slit provided between the antenna and the vacuum chamber, and processing the substrate in a state where the antenna cover is fixed by making both an inner side face of the slit and the antenna covered with an antenna cover, making a bottom face of the slit covered with a slit cover, supporting the antenna cover by the slit cover, and fixing the slit cover to a wall surface of the vacuum chamber.
摘要翻译：一种用于在真空室中产生等离子体并处理放置在基板电极上的基板的等离子体处理方法，所述等离子体是通过将频率为50MHz至3GHz的高频电源提供给与基板电极相对设置的天线而产生的通过向真空室供给气体并排出真空室的内部，真空室的内部被控制到规定的压力，该方法包括夹在天线和真空室之间的电介质板，天线和电介质板突出到真空室中，通过设置在天线和真空室之间的环形和凹槽来控制基板上的等离子体分布，并且通过使天线盖固定的状态来处理基板的狭缝和天线覆盖有天线盖，使狭缝的底面覆盖有狭缝c 通过狭缝盖支撑天线罩，并将狭缝盖固定到真空室的壁面。

7. 发明申请

US20080277771A1 Electronic Device Package Manufacturing Method and Electronic Device Package 有权
标题翻译：电子设备封装制造方法和电子器件封装
公开(公告)号：US20080277771A1
公开(公告)日：2008-11-13
申请号：US11883166
申请日：2006-01-26
申请人： Kazushi Higashi , Yukihiro Maegawa
发明人： Kazushi Higashi , Yukihiro Maegawa
IPC分类号： H01L23/48 , H01L21/52
CPC分类号： H03H9/1092 , H01L23/04 , H01L23/053 , H01L2224/92144 , H01L2924/01019 , H01L2924/01079 , H01L2924/09701 , H01L2924/1461 , H01L2924/00
摘要： By joining a lid member to a base member, internal electrodes put in contact with the lid member and an electronic device connected to the internal electrodes are placed in an internal space located in between the base member and the lid member. Then, by performing etching from a surface of the lid member on the side opposite from the base member by a prescribed method, through holes that reach the surface of the internal electrodes are formed. A conductive material is given to the through holes, and external electrodes connected to the internal electrodes are formed in a plane, completing a thin type electronic device package.
摘要翻译：通过将盖构件接合到基座构件，与盖构件接触的内部电极和连接到内部电极的电子装置被放置在位于基座构件和盖构件之间的内部空间中。然后，通过利用规定的方法从盖部件的与基部部件相反的一侧的表面进行蚀刻，形成到达内部电极表面的通孔。向通孔提供导电材料，并且连接到内部电极的外部电极形成在平面中，从而完成薄型电子器件封装。

8. 发明授权

US07638888B2 Semiconductor chip mounting substrate, semiconductor chip mounting body, semiconductor chip stacked module, and semiconductor chip mounting substrate manufacturing method 失效
标题翻译：半导体芯片安装基板，半导体芯片安装体，半导体芯片堆叠模块以及半导体芯片安装基板的制造方法
公开(公告)号：US07638888B2
公开(公告)日：2009-12-29
申请号：US12031363
申请日：2008-02-14
申请人： Naoki Suzuki , Akihisa Nakahashi , Yukihiro Maegawa
发明人： Naoki Suzuki , Akihisa Nakahashi , Yukihiro Maegawa
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L23/13 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2224/45014 , H01L2224/4899 , H01L2224/4903 , H01L2224/49051 , H01L2225/0651 , H01L2225/06572 , H01L2225/06593 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0106 , H01L2924/01078 , Y10T29/49128 , H01L2224/45099 , H01L2224/05599
摘要： There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate.
摘要翻译：提供了一种半导体芯片安装基板，包括：基板，其上形成有用于安装半导体芯片的安装区域和用于半导体芯片的层间连接的连接区域;以及多个在堆叠时对准的对准标记，设置在基板的周围或连接区域中，其中，作为用于加强多个对准标记之间的部分的加强区域的加强构件设置在基板上。

9. 发明申请

US20080197471A1 SEMICONDUCTOR CHIP MOUNTING SUBSTRATE, SEMICONDUCTOR CHIP MOUNTING BODY, SEMICONDUCTOR CHIP STACKED MODULE, AND SEMICONDUCTOR CHIP MOUNTING SUBSTRATE MANUFACTURING METHOD 失效
标题翻译：半导体芯片安装基板，半导体芯片安装体，半导体芯片堆叠模块和半导体芯片安装基板制造方法
公开(公告)号：US20080197471A1
公开(公告)日：2008-08-21
申请号：US12031363
申请日：2008-02-14
申请人： Naoki Suzuki , Akihisa Nakahashi , Yukihiro Maegawa
发明人： Naoki Suzuki , Akihisa Nakahashi , Yukihiro Maegawa
IPC分类号： H01L23/48 , H01L23/544 , H05K3/00
CPC分类号： H01L23/544 , H01L23/13 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2224/45014 , H01L2224/4899 , H01L2224/4903 , H01L2224/49051 , H01L2225/0651 , H01L2225/06572 , H01L2225/06593 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0106 , H01L2924/01078 , Y10T29/49128 , H01L2224/45099 , H01L2224/05599
摘要： There is provided a semiconductor chip mounting substrate including a substrate on which a mounting region for mounting a semiconductor chip and a connection region for interlayer connection of the semiconductor chip are formed, and a plurality of alignment marks for alignment at the time of stacking which are provided around or in the connection region on the substrate, wherein a reinforcing member as a reinforcing region for reinforcing a portion between the plurality of alignment marks is provided on the substrate.
摘要翻译：提供了一种半导体芯片安装基板，包括：基板，其上形成有用于安装半导体芯片的安装区域和用于半导体芯片的层间连接的连接区域;以及多个在堆叠时对准的对准标记，设置在基板的周围或连接区域中，其中，作为用于加强多个对准标记之间的部分的加强区域的加强构件设置在基板上。

10. 发明授权

US07615406B2 Electronic device package manufacturing method and electronic device package 有权
标题翻译：电子器件封装制造方法和电子器件封装
公开(公告)号：US07615406B2
公开(公告)日：2009-11-10
申请号：US11883166
申请日：2006-01-26
申请人： Kazushi Higashi , Yukihiro Maegawa
发明人： Kazushi Higashi , Yukihiro Maegawa
IPC分类号： H01L21/00
CPC分类号： H03H9/1092 , H01L23/04 , H01L23/053 , H01L2224/92144 , H01L2924/01019 , H01L2924/01079 , H01L2924/09701 , H01L2924/1461 , H01L2924/00
摘要： By joining a lid member to a base member, internal electrodes put in contact with the lid member and an electronic device connected to the internal electrodes are placed in an internal space located in between the base member and the lid member. By performing etching from a surface of the lid member on a side opposite from the base member by a prescribed method, through holes that reach the surface of the internal electrodes are formed. A conductive material is applied to the through holes, and external electrodes connected to the internal electrodes are formed in a plane, completing a thin type electronic device package.
摘要翻译：通过将盖构件接合到基座构件，与盖构件接触的内部电极和连接到内部电极的电子装置被放置在位于基座构件和盖构件之间的内部空间中。通过利用规定的方法从与盖体相反侧的表面进行蚀刻，形成到达内部电极表面的通孔。将导电材料施加到通孔，并且连接到内部电极的外部电极形成在平面中，从而完成薄型电子器件封装。

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