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1. 发明申请

US20060017181A1 Semiconductor memory device and semiconductor device group 有权
公开(公告)号：US20060017181A1
公开(公告)日：2006-01-26
申请号：US10988530
申请日：2004-11-16
申请人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
发明人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
IPC分类号： H01L31/109
CPC分类号： H01L27/1104 , G11C5/063 , G11C11/412 , H01L27/11 , Y10S257/903
摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

2. 发明授权

US07508692B2 Semiconductor memory device and semiconductor device group 有权
公开(公告)号：US07508692B2
公开(公告)日：2009-03-24
申请号：US11802812
申请日：2007-05-25
申请人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
发明人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
IPC分类号： G11C5/06
CPC分类号： H01L27/1104 , G11C5/063 , G11C11/412 , H01L27/11 , Y10S257/903
摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

3. 发明申请

US20070223271A1 Semiconductor memory device and semiconductor device group 有权
标题翻译：半导体存储器件和半导体器件组
公开(公告)号：US20070223271A1
公开(公告)日：2007-09-27
申请号：US11802812
申请日：2007-05-25
申请人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
发明人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C5/063 , G11C11/412 , H01L27/11 , Y10S257/903
摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.
摘要翻译：半导体器件包括第一CMOS反相器，第二CMOS反相器，第一传输晶体管和第二传输晶体管，其中第一和第二传输晶体管分别形成在由器件隔离区限定在半导体器件上的第一和第二器件区域中，为了彼此并联延伸，第一传输晶体管在第一器件区域上的第一位接触区域处与第一位线接触，第二传输晶体管在第二位线处与第二位线接触，第二位线在第二位接触区域处器件区域，其中第一位接触区域形成在第一器件区域中，使得所述位接触区域的中心朝向第二器件区域偏移，并且其中第二位接触区域形成在第二器件区域中，使得第二位接触区域的中心朝向第一器件区域偏移。

4. 发明申请

US20060177978A1 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20060177978A1
公开(公告)日：2006-08-10
申请号：US11139651
申请日：2005-05-31
申请人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L21/8244
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L27/11531 , H01L28/20
摘要： A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form a silicide block on the resistance element, and side wall spacers at both side surfaces of gate electrodes, and so on, of respective transistors, at the same time.
摘要翻译：作为绝缘膜的氧化硅膜，在除去抗蚀剂图案之后，通过例如热CVD法覆盖包括电阻元件的表面的硅基板的整个表面。处理该氧化硅膜，同时在电阻元件上形成硅化物块，以及在各个晶体管的栅电极的两侧表面的侧壁间隔物等。

5. 发明申请

US20060038240A1 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20060038240A1
公开(公告)日：2006-02-23
申请号：US11020257
申请日：2004-12-27
申请人： Tomohiko Tsutsumi , Toru Anezaki , Hideyuki Kojima , Taiji Ema
发明人： Tomohiko Tsutsumi , Toru Anezaki , Hideyuki Kojima , Taiji Ema
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L27/115 , H01L27/11 , H01L27/1104 , H01L27/11526 , H01L27/11546
摘要： An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.
摘要翻译：在p型Si衬底上形成元件隔离绝缘膜之后，在SRAM单元区域的N-LV区域中形成n型嵌入层。此后，形成p阱和n阱。在沟道掺杂层的形成中，也将与离子注入并联的SRAM单元区域的N-LV区域中的离子注入进入逻辑电路区域的N-LV。离子注入进一步进入SRAM单元区域的N-LV区域并与离子注入并入I / O区域的N-MV。

6. 发明授权

US08283729B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08283729B2
公开(公告)日：2012-10-09
申请号：US13010255
申请日：2011-01-20
申请人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
摘要翻译：半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

7. 发明申请

US20100238716A1 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE GROUP 有权
标题翻译：半导体存储器件和半导体器件组
公开(公告)号：US20100238716A1
公开(公告)日：2010-09-23
申请号：US12792115
申请日：2010-06-02
申请人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
发明人： Toru Anezaki , Tomohiko Tsutsumi , Tatsuji Araya , Hideyuki Kojima , Taiji Ema
IPC分类号： G11C11/00 , G11C11/34
CPC分类号： H01L27/1104 , G11C5/063 , G11C11/412 , H01L27/11 , Y10S257/903
摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.
摘要翻译：半导体器件包括第一CMOS反相器，第二CMOS反相器，第一传输晶体管和第二传输晶体管，其中第一和第二传输晶体管分别形成在由器件隔离区限定在半导体器件上的第一和第二器件区域中，为了彼此并联延伸，第一传输晶体管在第一器件区域上的第一位接触区域处与第一位线接触，第二传输晶体管在第二位线处与第二位线接触，第二位线在第二位接触区域处器件区域，其中第一位接触区域形成在第一器件区域中，使得所述位接触区域的中心朝向第二器件区域偏移，并且其中第二位接触区域形成在第二器件区域中，使得第二位接触区域的中心朝向第一器件区域偏移。

8. 发明申请

US20090224332A1 Semiconductor device 审中-公开
公开(公告)号：US20090224332A1
公开(公告)日：2009-09-10
申请号：US12320913
申请日：2009-02-09
申请人： Tomohiko Tsutsumi , Toru Anezaki , Hideyuki Kojima , Taiji Ema
发明人： Tomohiko Tsutsumi , Toru Anezaki , Hideyuki Kojima , Taiji Ema
IPC分类号： H01L27/11 , H01L21/8239
CPC分类号： H01L27/115 , H01L27/11 , H01L27/1104 , H01L27/11526 , H01L27/11546
摘要： An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.

9. 发明授权

US07135367B2 Manufacturing method of semiconductor device 有权
公开(公告)号：US07135367B2
公开(公告)日：2006-11-14
申请号：US11139651
申请日：2005-05-31
申请人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L21/8234 , H01L21/8244 , H01L21/20
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L27/11531 , H01L28/20
摘要： A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form a silicide block on the resistance element, and side wall spacers at both side surfaces of gate electrodes, and so on, of respective transistors, at the same time.

10. 发明授权

US08426267B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08426267B2
公开(公告)日：2013-04-23
申请号：US13010416
申请日：2011-01-20
申请人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
发明人： Tomohiko Tsutsumi , Taiji Ema , Hideyuki Kojima , Toru Anezaki
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L27/0629 , H01L21/823814 , H01L21/823857 , H01L27/0266 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
摘要翻译：半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

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