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    • 7. 发明授权
    • Method and apparatus for handling an interrupt from a real-time clock to increment a program clock
    • 用于处理来自实时时钟的中断以递增程序时钟的方法和装置
    • US06981165B2
    • 2005-12-27
    • US10233731
    • 2002-09-03
    • Mark D. Marik
    • Mark D. Marik
    • G06F1/14G06F1/12
    • G06F1/14
    • A method and apparatus for handling an interrupt from a real-time clock to increment a program clock in a computer system while compensating for missed interrupts due to contention on a system bus from a DMA controller or the like. In accordance with the invention, a count is stored representing a cumulative interval of time that has elapsed without a corresponding incrementing of the program clock. In response to an interrupt from the real-time clock, the processor transfers control to an interrupt handling routine, which determines the interval of time that has elapsed since the previous real-time clock interrupt and increments the cumulative interval of time by the actual interval of time that has elapsed since the previous real-time clock interrupt. If the cumulative interval of time is greater than an expected interval of time between real-time clock interrupts, the interrupt handling routine iteratively increments the program clock and decrements the cumulative interval of time to reflect incrementing of the program clock until the cumulative interval of time is less than the expected interval of time between real-time clock interrupts.
    • 一种用于处理来自实时时钟的中断以递增计算机系统中的程序时钟的方法和装置,同时补偿由于来自DMA控制器等的系统总线上的争用导致的中断。 根据本发明,存储表示在没有相应递增的程序时钟的情况下经过的累积时间间隔的计数。 响应于来自实时时钟的中断,处理器将控制器传送到中断处理例程,该中断处理程序确定从先前的实时时钟中断起经过的时间间隔,并将累积的时间间隔增加实际间隔 从上一次实时时钟中断开始的时间。 如果累积时间间隔大于实时时钟中断之间的期望时间间隔,则中断处理程序会迭代地增加程序时钟,并减少累积时间间隔,以反映程序时钟的增加,直到累积时间间隔 小于实时时钟中断之间的预期间隔时间。
    • 9. 发明授权
    • Method and apparatus for decoding two frequency (f/sf) data signals
    • 解码两个频率(f / 2f)数据信号的方法和装置
    • US5298897A
    • 1994-03-29
    • US822595
    • 1992-01-17
    • Clarence HarrisonMark D. MarikRoger L. Posthumus
    • Clarence HarrisonMark D. MarikRoger L. Posthumus
    • G06K7/00G06K7/08G11B20/10G11B20/14H04L25/49H04L27/14H03M5/12
    • G11B20/1419
    • A two-frequency data signal, also known as a biphase or F/2F signal, is accurately decoded by sampling the signal and digitizing the samples to provide a series of digital values representing the signal. An intelligent digital filter manipulates the digital values to decode the signal, by detecting the peaks in the sampled signal and decoding the signal by analyzing the location and amplitudes of the peaks. Only peaks which are outside a guard band may be detected. If the signal cannot be properly decoded with a wide guard band, the guard band may be repeatedly narrowed, until a minimum guard band is reached. Bits are identified by comparing the displacements between peaks to a bit cell width. An even number of displacements indicates a `0` bit, and an odd number of displacements indicates a `1` bit. After decoding, the bits are converted into bytes. Parity and longitudinal redundancy code checks are used to correct bad bits. During decoding, many indications of a degraded signal may be obtained. If a degraded signal is indicated, the host computer is notified, even though the signal was properly read. Card replacement can then be initiated at the first signs of signal degradation, before the data signal becomes unreadable.
    • 也称为双相或F / 2F信号的双频数据信号通过对信号进行采样并对样本进行数字化来精确地解码,以提供表示信号的一系列数字值。 智能数字滤波器通过检测采样信号中的峰值并通过分析峰值的位置和振幅对信号进行解码,来操纵数字值对信号进行解码。 只能检测到保护带外的峰值。 如果信号不能用宽的保护频带正确解码,则保护频段可能会被重复变窄,直到达到最小保护频带。 通过将峰之间的位移与位单元宽度进行比较来识别位。 偶数位移表示“0”位,奇数位移表示“1”位。 解码之后,这些位被转换成字节。 奇偶校验和纵向冗余码检查用于校正坏位。 在解码期间,可以获得许多恶化信号的指示。 如果指示了降级信号,即使信号被正确读取,也会通知主计算机。 然后,在数据信号变得不可读之前,可以在信号劣化的第一个迹象处启动卡替换。
    • 10. 发明申请
    • Concurrent Embedded Application Update
    • 并行嵌入式应用程序更新
    • US20110321023A1
    • 2011-12-29
    • US12822799
    • 2010-06-24
    • Michael D. HockerMark D. MarikJimmie R. Mayfield, JR.
    • Michael D. HockerMark D. MarikJimmie R. Mayfield, JR.
    • G06F9/445G06F9/44
    • G06F8/656
    • Providing concurrent embedded application updates comprising a first computer processor for executing a first embedded application, the executing generating a first plurality of processing threads, the first computer processor coupled to a first storage location and a second storage location. The first computer processor configured to accept and process instructions from a host system, receive one or more notifications indicating that a second embedded application has been successfully loaded into one of the first storage location and the second storage location, terminate execution of the first plurality of processing threads in response to receiving the one or more notifications, and execute the second embedded application while continuing to accept instructions from the host system and without restarting in response to receiving the one or more notifications.
    • 提供并发的嵌入式应用程序更新,包括用于执行第一嵌入式应用程序的第一计算机处理器,所述执行生成第一多个处理线程,所述第一计算机处理器耦合到第一存储位置和第二存储位置。 被配置为接受和处理来自主机系统的指令的第一计算机处理器,接收指示第二嵌入式应用已成功加载到第一存储位置和第二存储位置之一的一个或多个通知,终止第一多个 响应于接收到一个或多个通知来处理线程,并且在继续接受来自主机系统的指令的同时执行第二嵌入式应用,并且响应于接收到一个或多个通知而不重新启动。