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1. 发明授权

US06518654B1 Packages for semiconductor die 有权
公开(公告)号：US06518654B1
公开(公告)日：2003-02-11
申请号：US09834415
申请日：2001-04-13
申请人： Todd O. Bolken , Cary J. Baerlocher , David J. Corisis , Chad A. Cobbley
发明人： Todd O. Bolken , Cary J. Baerlocher , David J. Corisis , Chad A. Cobbley
IPC分类号： H01L2302
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/30107 , H05K3/303 , H05K3/305 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.

2. 发明授权

US07459773B2 Stackable ball grid array 有权
标题翻译：可堆叠球栅阵列
公开(公告)号：US07459773B2
公开(公告)日：2008-12-02
申请号：US11268095
申请日：2005-11-07
申请人： Todd O. Bolken , Cary J. Baerlocher , Chad A. Cobbley , David J. Corisis
发明人： Todd O. Bolken , Cary J. Baerlocher , Chad A. Cobbley , David J. Corisis
IPC分类号： H01L23/02
CPC分类号： H05K3/303 , H01L25/105 , H01L25/18 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/0002 , H01L2924/15311 , H01L2924/3011 , H05K2201/10515 , H05K2201/10734 , H05K2203/167 , Y02P70/613 , H01L2924/00
摘要： A memory package having a plurality of vertically stacked ball grid arrays. Each of the vertically stacked ball grid arrays has a memory chip coupled thereto. Further, each of the plurality of ball grid arrays includes non-metal mateable alignment features. Each of the plurality of ball grid arrays is coupled to another of the plurality of ball grid arrays to from the vertically stacked memory package.
摘要翻译：一种具有多个垂直堆叠的球栅阵列的存储器封装。每个垂直堆叠的球栅阵列具有与其耦合的存储芯片。此外，多个球栅阵列中的每一个包括非金属可对准的对准特征。多个球栅阵列中的每一个耦合到多个球栅阵列中的另一个，以从垂直堆叠的存储器封装。

3. 发明授权

US06329220B1 Packages for semiconductor die 有权
标题翻译：封装半导体芯片
公开(公告)号：US06329220B1
公开(公告)日：2001-12-11
申请号：US09448072
申请日：1999-11-23
申请人： Todd O. Bolken , Cary J. Baerlocher , David J. Corisis , Chad A. Cobbley
发明人： Todd O. Bolken , Cary J. Baerlocher , David J. Corisis , Chad A. Cobbley
IPC分类号： H01L2144
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/30107 , H05K3/303 , H05K3/305 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.
摘要翻译：球栅阵列组件包括包封模具和包括模具附接到其上的基板的一部分的封装盖，包括基板的边缘。通过盖子封装衬底边缘可以减少水分或其他污染物渗透到衬底中。该盖包括延伸以接触球栅阵列组件所连接的电路板的肋。使用这样的肋，在焊接期间保持电路板和基板之间的平坦度。

4. 发明授权

US06462273B1 Semiconductor card and method of fabrication 有权
标题翻译：半导体卡和制造方法
公开(公告)号：US06462273B1
公开(公告)日：2002-10-08
申请号：US09809781
申请日：2001-03-16
申请人： David J. Corisis , Todd O. Bolken
发明人： David J. Corisis , Todd O. Bolken
IPC分类号： H05K328
CPC分类号： H05K5/026 , G06K19/077 , H01L2224/05554 , H01L2224/49171 , H01L2224/49175 , H01L2924/181 , H05K5/065 , H01L2924/00012
摘要： A semiconductor card includes a printed circuit substrate and one or more semiconductor components, such as dice or packages, mounted to the substrate. The substrate is initially a segment of a strip containing several substrates. The substrate is defined by a peripheral opening in the strip, and is connected to the strip by connecting segments. The card also includes a plastic body molded to the substrate and having notches that initially align with the connecting segments. The notches provide access for severing the connecting segments, and also enclose any slivers of substrate material resulting from severing of the connecting segments. A method for fabricating the package includes the steps of providing the strip, and providing a molding apparatus configured to mold the plastic body to the substrate. The molding apparatus includes pins configured to contact the connecting segments to form the notches. A system for performing the method includes the strip, the molding apparatus and a punch apparatus for severing the connecting segments.
摘要翻译：半导体卡包括安装到基板上的印刷电路基板和一个或多个半导体部件，例如芯片或封装。衬底最初是包含几个衬底的条的段。衬底由条带中的周边开口限定，并且通过连接段连接到条带。该卡还包括模塑到基底上的塑料体，并且具有最初与连接段对准的凹口。切口提供切断连接段的通路，并且还包围由连接段断开而导致的任何基板材料片。制造包装的方法包括以下步骤：提供条带，并提供被配置成将塑料本体模塑到基底上的成型装置。成型设备包括构造成接触连接段以形成凹口的销。用于执行该方法的系统包括条，成型装置和用于切断连接段的冲压装置。

5. 发明授权

US06395579B2 Controlling packaging encapsulant leakage 有权
标题翻译：控制包装密封剂泄漏
公开(公告)号：US06395579B2
公开(公告)日：2002-05-28
申请号：US09789892
申请日：2001-02-21
申请人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
发明人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
IPC分类号： H01L2144
CPC分类号： H01L23/3107 , H01L21/565 , H01L23/3157 , H01L23/4985 , H01L24/48 , H01L2224/05599 , H01L2224/4824 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.
摘要翻译：集成电路封装可以部分地形成有封装区域。可以通过提供在封装区域和关键部件所在的区域之间收集密封剂流出物的空腔来防止密封剂在临界电气元件上的流出。在本发明的一个实施例中，表面可以包括由阻焊剂覆盖的第一部分，其具有由接合焊盘填充的区域和被封装的第二部分。通过在接近第二部分的阻焊剂中形成开口以在其到达接合焊盘之前收集密封剂来防止接合焊盘上的封装流动。

6. 发明授权

US06521980B1 Controlling packaging encapsulant leakage 有权
公开(公告)号：US06521980B1
公开(公告)日：2003-02-18
申请号：US09679095
申请日：2000-10-04
申请人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
发明人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
IPC分类号： H01L2348
CPC分类号： H01L23/3107 , H01L21/565 , H01L23/3157 , H01L23/4985 , H01L24/48 , H01L2224/05599 , H01L2224/4824 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

7. 发明授权

US06210992B1 Controlling packaging encapsulant leakage 有权
标题翻译：控制包装密封剂泄漏
公开(公告)号：US06210992B1
公开(公告)日：2001-04-03
申请号：US09386971
申请日：1999-08-31
申请人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
发明人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
IPC分类号： H01L2144
CPC分类号： H01L23/3107 , H01L21/565 , H01L23/3157 , H01L23/4985 , H01L24/48 , H01L2224/05599 , H01L2224/4824 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.
摘要翻译：集成电路封装可以部分地形成有封装区域。可以通过提供在封装区域和关键部件所在的区域之间收集密封剂流出物的空腔来防止密封剂在临界电气元件上的流出。在本发明的一个实施例中，表面可以包括由阻焊剂覆盖的第一部分，其具有由接合焊盘填充的区域和被封装的第二部分。通过在接近第二部分的阻焊剂中形成开口以在其到达接合焊盘之前收集密封剂来防止接合焊盘上的封装流动。

8. 发明授权

US07239029B2 Packages for semiconductor die 有权
标题翻译：封装半导体芯片
公开(公告)号：US07239029B2
公开(公告)日：2007-07-03
申请号：US10340331
申请日：2003-01-09
申请人： Todd O. Bolken , Cary J. Baerlocher , David J. Corisis , Chad A. Cobbley
发明人： Todd O. Bolken , Cary J. Baerlocher , David J. Corisis , Chad A. Cobbley
IPC分类号： H01L23/28
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/30107 , H05K3/303 , H05K3/305 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.
摘要翻译：球栅阵列组件包括包封模具和包括模具附接到其上的基板的一部分的封装盖，包括基板的边缘。通过盖子封装衬底边缘可以减少水分或其他污染物渗透到衬底中。该盖包括延伸以接触球栅阵列组件所连接的电路板的肋。使用这样的肋，在焊接期间保持电路板和基板之间的平坦度。

9. 发明授权

US07144245B2 Packages for semiconductor die 有权
公开(公告)号：US07144245B2
公开(公告)日：2006-12-05
申请号：US10731995
申请日：2003-12-09
申请人： Todd O. Bolken , Cary J. Baerlocher , David J. Corisis , Chad A. Cobbley
发明人： Todd O. Bolken , Cary J. Baerlocher , David J. Corisis , Chad A. Cobbley
IPC分类号： B29B11/06
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/30107 , H05K3/303 , H05K3/305 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.

10. 发明授权

US07101730B2 Method of manufacturing a stackable ball grid array 有权
标题翻译：制造可堆叠球栅阵列的方法
公开(公告)号：US07101730B2
公开(公告)日：2006-09-05
申请号：US10919090
申请日：2004-08-16
申请人： Todd O. Bolken , Cary J. Baerlocher , Chad A. Cobbley , David J. Corisis
发明人： Todd O. Bolken , Cary J. Baerlocher , Chad A. Cobbley , David J. Corisis
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/4763
CPC分类号： H05K3/303 , H01L25/105 , H01L25/18 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/0002 , H01L2924/15311 , H01L2924/3011 , H05K2201/10515 , H05K2201/10734 , H05K2203/167 , Y02P70/613 , H01L2924/00
摘要： A method of manufacturing a stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to a preformed packages which have alignment features to allow for the stacking of the ball grid arrays. The alignment features are used to align and orient each package with respect to an adjacent package, substrate or printed circuit board. The alignment features also support the weight of the adjacent package during solder ball reflow to maintain stack height and parallelism between packages. Each memory device is serially connected to the adjacent memory device through the vias and solder balls on each package.
摘要翻译：使用球栅阵列技术制造可堆叠封装以创建3维存储器阵列的方法。具体地，存储器芯片耦合到具有对准特征以允许球栅阵列的堆叠的预成型封装。对准特征用于相对于相邻的封装，衬底或印刷电路板对准和定向每个封装。对准特征还支持焊球回流期间相邻封装的重量，以保持堆叠高度和封装之间的平行度。每个存储器件通过每个封装上的通孔和焊球串联连接到相邻的存储器件。

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