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1. 发明授权

US5920882A Programmable circuit assembly and methods for high bandwidth data processing 失效
标题翻译：可编程电路组件和高带宽数据处理方法
公开(公告)号：US5920882A
公开(公告)日：1999-07-06
申请号：US752940
申请日：1996-11-21
申请人： Toby D. Bennett , James W. Bishop , Donald J. Davis , Jonathan C. Harris
发明人： Toby D. Bennett , James W. Bishop , Donald J. Davis , Jonathan C. Harris
IPC分类号： G06F15/78 , G06F13/00
CPC分类号： G06F15/7867
摘要： A programmable circuit assembly and methods for high bandwidth data processing. The assembly includes an array of in-circuit programmable logic packages interconnected with an array of memory packages, allowing for elastic buffering of data in a variety of directions. Each programmable package includes package leads, a memory, and output drivers. Each output driver is connected to a respective package lead, which is configured to generate a logic function defined by programming data stored in the memory. A method includes storing programming data for operating the assembly to send signals on different paths between a programmable package and a memory package.
摘要翻译：一种用于高带宽数据处理的可编程电路组件和方法。该组件包括与存储器封装阵列互连的在线可编程逻辑封装阵列，允许在各种方向弹性缓冲数据。每个可编程包装包括封装引线，存储器和输出驱动器。每个输出驱动器连接到相应的封装引线，其被配置为生成由存储在存储器中的编程数据定义的逻辑功能。一种方法包括存储用于操作组件以在可编程包和存储器包之间的不同路径上发送信号的编程数据。

2. 发明授权

US06122670A Apparatus and method for constructing data for transmission within a reliable communication protocol by performing portions of the protocol suite concurrently 失效
标题翻译：通过同时执行协议组的部分，在可靠通信协议内构建用于传输的数据的装置和方法
公开(公告)号：US06122670A
公开(公告)日：2000-09-19
申请号：US960837
申请日：1997-10-30
申请人： Toby D. Bennett , Donald J. Davis , Jonathan C. Harris , Ian D. Miller
发明人： Toby D. Bennett , Donald J. Davis , Jonathan C. Harris , Ian D. Miller
IPC分类号： H04L29/06 , H04L29/08 , G06F13/38 , G06F15/17
CPC分类号： H04L29/06 , H04L69/161 , H04L69/163 , H04L69/12 , H04L69/16 , H04L69/32
摘要： A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.
摘要翻译：一种用可靠通信协议发送和接收数据的系统和方法。该系统包括在具有背板的节点上的计算机，插入到背板中的CPU板，用于CPU的软件指令以及插入到背板中的专用网卡。 CPU板，软件和网卡用于实现TCP / IP协议套件。网卡或板包括从物理层接收数据包的接口，以及用于通过网络层软件解封装和路由TCP段之前验证TCP校验和的电路。它还包括自动准备由接收计算机发送到发送计算机的确认信号的电路。它还包括用于计算从发送计算机到接收计算机的输出信号上的错误检测码的电路。

3. 发明授权

US06345302B1 System for transmitting and receiving data within a reliable communications protocol by concurrently processing portions of the protocol suite 失效
标题翻译：用于通过同时处理协议组的部分在可靠通信协议内发送和接收数据的系统
公开(公告)号：US06345302B1
公开(公告)日：2002-02-05
申请号：US09641762
申请日：2000-08-21
申请人： Toby D. Bennett , Donald J. Davis , Jonathan C. Harris , Ian D. Miller
发明人： Toby D. Bennett , Donald J. Davis , Jonathan C. Harris , Ian D. Miller
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/163 , H04L69/32
摘要： A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.
摘要翻译：一种用可靠通信协议发送和接收数据的系统和方法。该系统包括在具有背板的节点上的计算机，插入到背板中的CPU板，用于CPU的软件指令以及插入到背板中的专用网卡。 CPU板，软件和网卡用于实现TCP / IP协议套件。网卡或板包括从物理层接收数据包的接口，以及用于通过网络层软件解封装和路由TCP段之前验证TCP校验和的电路。它还包括自动准备由接收计算机发送到发送计算机的确认信号的电路。它还包括用于计算从发送计算机到接收计算机的输出信号上的错误检测码的电路。

4. 发明授权

US06230307B1 System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects 失效
标题翻译：用于对现场可编程门阵列（FPGA）和相关重配置资源进行硬件编程的系统和方法，如同通过创建硬件对象是软件一样
公开(公告)号：US06230307B1
公开(公告)日：2001-05-08
申请号：US09013186
申请日：1998-01-26
申请人： Donald J. Davis , Toby D. Bennett , Jonathan C. Harris , Ian D. Miller , Stephen G. Edwards
发明人： Donald J. Davis , Toby D. Bennett , Jonathan C. Harris , Ian D. Miller , Stephen G. Edwards
IPC分类号： G06F1750
CPC分类号： G06F17/5054
摘要： A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.
摘要翻译：一种用于通过创建实现应用级功能，操作系统功能和硬件功能的硬件对象来编程现场可编程门阵列和相关可重配置资源的硬件的方法和系统，如同它们是软件一样。通过高级软件结构进一步控制和执行硬件对象并管理可重新配置的资源，使得针对当前执行的任务优化可重新配置的资源。

5. 发明授权

US07086047B1 Determining hardware generated by high level language compilation through loop optimizations 有权
标题翻译：通过循环优化确定高级语言编译生成的硬件
公开(公告)号：US07086047B1
公开(公告)日：2006-08-01
申请号：US10310362
申请日：2002-12-04
申请人： Stephen G. Edwards , Donald J. Davis , Jonathan C. Harris , James E. Jensen , Andreas B. Kollegger , Ian D. Miller
发明人： Stephen G. Edwards , Donald J. Davis , Jonathan C. Harris , James E. Jensen , Andreas B. Kollegger , Ian D. Miller
IPC分类号： G06F9/45
CPC分类号： G06F17/5054 , G06F8/443 , G06F8/447
摘要： A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language (100) and identifying a loop construct within the language independent model (705). A determination can be made as to whether the loop construct is bounded (725). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences 735). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique (740, 755).
摘要翻译：一种处理以通用编程语言编写以确定程序的硬件表示的程序的方法可以包括生成以通用编程语言（100）编写的程序的语言无关模型，并识别独立于语言的环路结构型号（705）。可以确定循环结构是否是有界的（725）。如果是，则可以根据存储的用户偏好735选择循环处理技术来展开循环结构。循环结构可以在所选择的环路处理技术（740,755）中指定的与语言无关的模型中复制。

6. 发明授权

US07111274B1 Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations 有权
标题翻译：调度由高级语言编译生成的硬件，以保留源代码设计实现的功能
公开(公告)号：US07111274B1
公开(公告)日：2006-09-19
申请号：US10310260
申请日：2002-12-04
申请人： Stephen G. Edwards , Donald J. Davis , Jonathan C. Harris , Andreas B. Kollegger , Ian D. Miller , Christopher R. S. Schanck , Yung-Sheng Yu
发明人： Stephen G. Edwards , Donald J. Davis , Jonathan C. Harris , Andreas B. Kollegger , Ian D. Miller , Christopher R. S. Schanck , Yung-Sheng Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (100) and identifying data input to each component specified in the language independent model to determine a latency for each component (220, 225). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (230). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself (235).
摘要翻译：一种处理通用的高级语言程序以确定程序的硬件表示的方法可以包括编译通用的高级语言程序以生成不依赖于语言的模型（100），并且识别输入到指定的每个组件的数据在语言独立模型中确定每个组件的延迟（220,225）。可以注释语言无关模型的组件以产生控制信号，使得当控制和有效数据都到达组件（230）时，每个组件被激活。每个组件还可以用来自组件的控制信号的等待时间的导出等待时间和从组件本身的执行确定的等待时间来注释（235）。

7. 发明授权

US07509619B1 Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages 有权
标题翻译：自动生成以高级语言捕获的设计的多级处理管道硬件实现
公开(公告)号：US07509619B1
公开(公告)日：2009-03-24
申请号：US11159085
申请日：2005-06-22
申请人： Ian D. Miller , Jonathan C. Harris
发明人： Ian D. Miller , Jonathan C. Harris
IPC分类号： G06F17/50 , G06F9/44 , G06F9/45
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.
摘要翻译：基于高级语言（HLL）程序创建多级硬件实现的方法可以包括从HLL程序生成与语言无关的模型（LIM），其中LIM指定多个状态资源并确定第一和最后一个访问多个状态资源中的每一个。该方法还可以包括从LIM识别多个处理阶段，其中每个处理阶段由对多个状态资源之一的第一次和最后访问定义。 LIM中的停顿点可以包含在每个第一次访问中。 LIM可以转换为指定多阶段硬件实现的调度硬件描述。

8. 发明授权

US07222314B1 Generation of a hardware interface for a software procedure 有权
标题翻译：生成软件程序的硬件接口
公开(公告)号：US07222314B1
公开(公告)日：2007-05-22
申请号：US11008849
申请日：2004-12-09
申请人： Ian D. Miller , Jonathan C. Harris , Stephen G. Edwards
发明人： Ian D. Miller , Jonathan C. Harris , Stephen G. Edwards
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Generation of a hardware interface specification for a software procedure. In one embodiment, an HDL description is generated for a first memory, at least one first state machine, a second memory, at least one second state machine, and an activation signal. The first memory stores input data corresponding to a plurality of data values consumed by the software procedure. The first state machine receives the input data and stores the input data in the first memory, and at least one of the at least one first state machines receives a plurality of the data values. The second memory stores output data corresponding to at least one data value produced by the software procedure. The second state machine reads the output data from the second memory and sends the output data.
摘要翻译：生成软件程序的硬件接口规范。在一个实施例中，为第一存储器，至少一个第一状态机，第二存储器，至少一个第二状态机和激活信号生成HDL描述。第一存储器存储与由软件过程消耗的多个数据值相对应的输入数据。第一状态机接收输入数据并将输入数据存储在第一存储器中，并且至少一个第一状态机中的至少一个接收多个数据值。第二存储器存储对应于由软件过程产生的至少一个数据值的输出数据。第二状态机从第二存储器读取输出数据并发送输出数据。

9. 发明授权

US06877150B1 Method of transforming software language constructs to functional hardware equivalents 有权
标题翻译：将软件语言结构转换为功能硬件等效的方法
公开(公告)号：US06877150B1
公开(公告)日：2005-04-05
申请号：US10310520
申请日：2002-12-04
申请人： Ian D. Miller , Stephen G. Edwards , Jonathan C. Harris , James E. Jensen , Andreas B. Kollegger , Christopher R. S. Schanck , Conor C. Wu
发明人： Ian D. Miller , Stephen G. Edwards , Jonathan C. Harris , James E. Jensen , Andreas B. Kollegger , Christopher R. S. Schanck , Conor C. Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of designing an integrated circuit using a general purpose programming language can include identifying (105) a number of instances of each class allocated in a programmatic design implemented using the general purpose programming language and modeling (110) the global memory of the programmatic design. A data flow between the modeled global memory and instructions of the programmatic design which access object fields can be determined (115) and access to the modeled global memory can be scheduled (120). The programmatic design can be translated (125) into a hardware description of the integrated circuit using the modeled global memory, the data flow, and the scheduled memory access.
摘要翻译：使用通用编程语言设计集成电路的方法可以包括识别（105）使用通用编程语言实现的编程设计中分配的每个类的多个实例，并对编程设计的全局存储器进行建模（110）。可以确定建模的全局存储器和访问对象字段的编程设计的指令之间的数据流（115），并且可以调度对建模的全局存储器的访问（120）。可以使用建模的全局存储器，数据流和调度的存储器访问将编程设计（125）转换为集成电路的硬件描述。

10. 发明授权

US08139810B2 Motorcycle speaker system 有权
标题翻译：摩托车扬声器系统
公开(公告)号：US08139810B2
公开(公告)日：2012-03-20
申请号：US12844634
申请日：2010-07-27
申请人： Mark J. Armitage , Jonathan C. Harris , Robert Hazelwood , Scott Hein , Benjamin H. Hodge, IV , William N. House , Thomas E. Strunsee
发明人： Mark J. Armitage , Jonathan C. Harris , Robert Hazelwood , Scott Hein , Benjamin H. Hodge, IV , William N. House , Thomas E. Strunsee
IPC分类号： H04R1/02 , H04B1/00
CPC分类号： B60R11/0217 , B62J7/04 , B62J9/00 , H04R1/2819 , H04R5/02
摘要： A motorcycle having an open-air cockpit area and a seat configured to receive a rider and position the rider within the open-air cockpit area. A luggage container defines a substantially enclosed cargo volume, and the luggage container is configured to open to provide selective access to the cargo volume. A speaker is configured to output sound in response to signals from a source. A speaker enclosure at least partially encloses the speaker. A bass-reflex passage couples an interior space of the sparker enclosure and the cargo volume of the luggage container.
摘要翻译：一种具有露天驾驶舱区域和座椅的摩托车，其配置成接收骑手并将驾驶员定位在露天驾驶舱区域内。行李容器限定基本封闭的货物体积，并且行李箱容器被配置为打开以提供对货物容积的选择性接近。扬声器被配置为响应于来自源的信号输出声音。扬声器外壳至少部分地包围扬声器。低音反射通道连接火花塞外壳的内部空间和行李箱的货物容积。

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