专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110101371A1 Gallium nitride semiconductor 审中-公开
标题翻译：氮化镓半导体
公开(公告)号：US20110101371A1
公开(公告)日：2011-05-05
申请号：US12930179
申请日：2010-12-30
申请人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Rick Stall
发明人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Rick Stall
IPC分类号： H01L29/20
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/475
摘要： A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
摘要翻译：由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层，其厚度介于1微米与6微米之间，设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。优化了层厚度和细长指状物的长度和宽度，以实现具有大于500伏特的击穿电压，超过1安培的电流容量和小于3伏特的正向电压的器件。

2. 发明申请

US20090035925A1 Gallium Nitride Semiconductor Device 有权
标题翻译：氮化镓半导体器件
公开(公告)号：US20090035925A1
公开(公告)日：2009-02-05
申请号：US12249099
申请日：2008-10-10
申请人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
发明人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
IPC分类号： H01L21/425
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/475
摘要： A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
摘要翻译：由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层，其厚度介于1微米与6微米之间，设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。优化了层厚度和细长指状物的长度和宽度，以实现具有大于500伏特的击穿电压，超过1安培的电流容量和小于3伏特的正向电压的器件。

3. 发明授权

US07436039B2 Gallium nitride semiconductor device 失效
标题翻译：氮化镓半导体器件
公开(公告)号：US07436039B2
公开(公告)日：2008-10-14
申请号：US11030554
申请日：2005-01-06
申请人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
发明人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
IPC分类号： H01L23/58
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/475
摘要： A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
摘要翻译：由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层，其厚度介于1微米与6微米之间，设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。优化了层厚度和细长指状物的长度和宽度，以实现具有大于500伏特的击穿电压，超过1安培的电流容量和小于3伏特的正向电压的器件。

4. 发明授权

US07863172B2 Gallium nitride semiconductor device 有权
标题翻译：氮化镓半导体器件
公开(公告)号：US07863172B2
公开(公告)日：2011-01-04
申请号：US12249099
申请日：2008-10-10
申请人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
发明人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/475
摘要： A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
摘要翻译：由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层，其厚度介于1微米与6微米之间，设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。优化了层厚度和细长指状物的长度和宽度，以实现具有大于500伏特的击穿电压，超过1安培的电流容量和小于3伏特的正向电压的器件。

5. 发明申请

US20060145283A1 Gallium nitride semiconductor device 失效
标题翻译：氮化镓半导体器件
公开(公告)号：US20060145283A1
公开(公告)日：2006-07-06
申请号：US11030554
申请日：2005-01-06
申请人： TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard Stall
发明人： TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard Stall
IPC分类号： H01L27/095 , H01L21/338
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/475
摘要： A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
摘要翻译：由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层，其厚度介于1微米与6微米之间，设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。优化了层厚度和细长指状物的长度和宽度，以实现具有大于500伏特的击穿电压，超过1安培的电流容量和小于3伏特的正向电压的器件。

6. 发明申请

US20100140627A1 Package for Semiconductor Devices 审中-公开
标题翻译：半导体器件封装
公开(公告)号：US20100140627A1
公开(公告)日：2010-06-10
申请号：US12575717
申请日：2009-10-08
申请人： Bryan S. Shelton , Marek K. Pabisz , TingGang Zhu , Linlin Liu , Boris Peres
发明人： Bryan S. Shelton , Marek K. Pabisz , TingGang Zhu , Linlin Liu , Boris Peres
IPC分类号： H01L23/495 , H01L29/20
CPC分类号： H01L23/49562 , H01L21/56 , H01L23/3107 , H01L23/562 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/2919 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/49 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/20755 , H01L2924/2076 , H01L2924/3011 , H01L2924/00014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012
摘要： A packaged semiconductor device including a semiconductor die mounted on a header of a leadframe. A plurality of spaced external conductors extends from the header and at least one of the external conductors has a bond wire post at one end thereof such that a bonding wire extends between the bond wire post and the semiconductor die. The package device also includes a housing, which encloses the semiconductor die, the header, the bonding wire and the bonding wire post resulting in an insulated packaged device.
摘要翻译：一种封装的半导体器件，包括安装在引线框的头部上的半导体管芯。多个间隔开的外部导体从集管延伸，并且至少一个外部导体在其一端具有接合线柱，使得接合线在接合线柱和半导体管芯之间延伸。包装装置还包括壳体，其包围半导体管芯，集管，接合线和接合线柱，形成绝缘的封装装置。

7. 发明申请

US20060151868A1 Package for gallium nitride semiconductor devices 审中-公开
标题翻译：氮化镓半导体器件封装
公开(公告)号：US20060151868A1
公开(公告)日：2006-07-13
申请号：US11032666
申请日：2005-01-10
申请人： TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Boris Peres , Alex Ceruzzi
发明人： TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Boris Peres , Alex Ceruzzi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3107 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/49171 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/20755 , H01L2924/2076 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/43 , H01L2924/01006
摘要： A packaged semiconductor device, in particular a gallium nitride semiconductor structure including a lower semiconductor layer and an upper semiconductor layer disposed over a portion of the lower semiconductor layer. The semiconductor structure includes a plurality of mesas projecting upwardly from the lower layer, each of the mesas including a portion of the upper layer and defining an upper contact surface separated form adjacent mesas by a portion of the lower layer surface. The device further includes a die mounting support, wherein the bottom surface of the die is attached to the top surface of the die mounting support; and a plurality of spaced external conductors extending from the support, at least once of said spaced external conductors having a bond wire post at one end thereof; with a bonding wire extending between the bond wire post and a contact region to the top surface of the plurality of mesas.
摘要翻译：封装的半导体器件，特别是包括下半导体层和设置在下半导体层的一部分上的上半导体层的氮化镓半导体结构。半导体结构包括从下层向上突出的多个台面，每个台面包括上层的一部分，并且限定由下层表面的一部分与相邻台面分开的上接触表面。该装置还包括模具安装支撑件，其中模具的底表面附接到模具安装支撑件的顶表面; 以及从所述支撑件延伸的多个间隔开的外部导体，所述间隔开的外部导体中的至少一个在其一端具有接合线柱; 其中接合线在接合线柱和与多个台面的顶表面之间的接触区域之间延伸。

8. 发明申请

US20070093037A1 Vertical structure semiconductor devices and method of fabricating the same 审中-公开
标题翻译：垂直结构半导体器件及其制造方法
公开(公告)号：US20070093037A1
公开(公告)日：2007-04-26
申请号：US11586948
申请日：2006-10-25
申请人： TingGang Zhu , Marek Pabisz , Milan Pophristic
发明人： TingGang Zhu , Marek Pabisz , Milan Pophristic
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/66143 , H01L29/861 , H01L33/0079 , H01L33/32
摘要： The present invention provides a vertical structure semiconductor device and method of fabricating the same. The method comprises providing a sapphire substrate bonded to a bottom surface of a semiconductor wafer, and a metal coated to the top surface of the semiconductor wafer. The method also comprises securely bonding a thermal and electrical conductive substrate to the wafer and removing the sapphire substrate from the wafer by laser lift-off to expose the bottom surface of the wafer. Furthermore, a metal is deposited to the exposed bottom surface of the wafer.
摘要翻译：本发明提供一种垂直结构半导体器件及其制造方法。该方法包括提供粘合到半导体晶片的底表面的蓝宝石衬底和涂覆到半导体晶片的顶表面的金属。该方法还包括将热导电基板和导电基板牢固地接合到晶片上，并通过激光剥离从晶片去除蓝宝石基板以暴露晶片的底表面。此外，金属沉积到晶片的暴露的底表面。

9. 发明申请

US20120282762A1 Method For Forming Gallium Nitride Semiconductor Device With Improved Forward Conduction 有权
标题翻译：用于形成具有改进的正向传导的氮化镓半导体器件的方法
公开(公告)号：US20120282762A1
公开(公告)日：2012-11-08
申请号：US13553237
申请日：2012-07-19
申请人： TingGang Zhu
发明人： TingGang Zhu
IPC分类号： H01L21/329 , H01L21/20
CPC分类号： H01L29/2003 , H01L29/0692 , H01L29/417 , H01L29/872
摘要： A method for forming a gallium nitride based semiconductor diode includes forming Schottky contacts on the upper surface of mesas formed in a semiconductor body formed on a substrate. Ohmic contacts are formed on the lower surface of the semiconductor body. In one embodiment, an insulating layer is formed over the Schottky and ohmic contacts and vias are formed in the insulating layer to the Schottky and ohmic contacts to form the anode and cathode electrodes. In another embodiment, vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the ohmic contacts. An anode electrode is formed in electrical contact with the Schottky contacts. A cathode electrode is formed in electrical contact with the ohmic contacts on the backside of the substrate.
摘要翻译：形成氮化镓基半导体二极管的方法包括在形成在基板上的半导体本体中形成的台面的上表面上形成肖特基触点。在半导体本体的下表面上形成欧姆接触。在一个实施例中，在肖特基和欧姆接触之上形成绝缘层，并且在绝缘层中形成通孔至肖特基和欧姆接触以形成阳极和阴极电极。在另一个实施例中，在绝缘层中形成通孔至肖特基接触，并且在半导体本体中形成通孔至欧姆接触。形成与肖特基接触电接触的阳极电极。阴极电极形成为与衬底背面上的欧姆接触电接触。

10. 发明申请

US20110278589A1 Gallium Nitride Semiconductor Device With Improved Forward Conduction 有权
标题翻译：具有改进的正向传导的氮化镓半导体器件
公开(公告)号：US20110278589A1
公开(公告)日：2011-11-17
申请号：US13191325
申请日：2011-07-26
申请人： TingGang Zhu
发明人： TingGang Zhu
IPC分类号： H01L29/872
CPC分类号： H01L29/2003 , H01L29/0692 , H01L29/417 , H01L29/872
摘要： A gallium nitride based semiconductor diode includes a substrate, a semiconductor body including a first heavily doped GaN layer and a second lightly doped GaN layer. The semiconductor body includes mesas projecting upwardly from a lower surface where each of the mesas includes the second GaN layer and a portion of the first GaN layer. Schottky contacts are formed on the upper surface of the mesas and ohmic contacts are formed on the lower surface of the semiconductor body. An insulating layer is formed over the Schottky and ohmic contacts. Vias are formed in the insulating layer to the Schottky contacts and vias are formed in the semiconductor body to the Ohmic contacts. An anode electrode is formed in a first metal pad in electrical contact with the Schottky contacts. A cathode electrode is formed in a second metal pad in electrical contact with the ohmic contacts.
摘要翻译：氮化镓基半导体二极管包括衬底，包括第一重掺杂GaN层和第二轻掺杂GaN层的半导体本体。半导体主体包括从下表面向上突出的台面，其中每个台面包括第二GaN层和第一GaN层的一部分。在台面的上表面上形成肖特基接触，并且在半导体本体的下表面上形成欧姆接触。绝缘层形成在肖特基和欧姆接触之上。在绝缘层中形成有与肖特基触点相对的通孔，并且在半导体本体中形成通孔至欧姆接触。阳极电极形成在与肖特基接触件电接触的第一金属焊盘中。阴极电极形成在与欧姆接触件电接触的第二金属焊盘中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式