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    • 3. 发明授权
    • Two-port memory capable of simultaneous read and write
    • 双端口存储器,能够同时读写
    • US08959291B2
    • 2015-02-17
    • US12974943
    • 2010-12-21
    • Ting Zhou
    • Ting Zhou
    • G06F12/08G11C8/16G06F12/06G11C7/10
    • G11C8/16G06F12/06G11C7/1075Y02D10/13
    • Described embodiments provide a multi-port memory system that has a plurality of memory banks and an equal number of mapping memory banks, each one of the data memory banks corresponding to one of the mapping memory banks. The multi-port memory reads, from one of the mapping memory banks selected by a read logical bank number, a read physical bank number identifying which one of the data memory banks data is to be read. The memory system also calculates, from at least one physical bank number read from the mapping memory banks other than the mapping memory bank selected by the read logical bank number, a write physical bank number indicating which one of the data memory banks is to be written. The calculation uses a hash of the physical bank numbers, such as by using an Exclusive-OR. This arrangement allows for simultaneous read/write access of the memory with fixed latency.
    • 描述的实施例提供一种多端口存储器系统,该多端口存储器系统具有多个存储器组和相等数目的映射存储器组,每个数据存储器库对应于一个映射存储器组。 多端口存储器从由读取的逻辑库号选择的映射存储体之一读取识别要读取哪个数据存储体数据的读取物理库号。 存储器系统还从从读取的逻辑库号选择的映射存储体之外的映射存储体读取的至少一个物理存储体号计算指示要写入哪个数据存储器组的写入物理存储体号 。 计算使用物理库号的散列,例如使用“异或”。 这种安排允许以固定的延迟同时对存储器进行读/写访问。
    • 8. 发明授权
    • High speed packet FIFO input buffers for switch fabric with speedup and retransmit
    • 用于交换结构的高速分组FIFO输入缓冲区,具有加速和重传
    • US08243737B2
    • 2012-08-14
    • US12729226
    • 2010-03-22
    • Ting ZhouSheng LiuEphrem Wu
    • Ting ZhouSheng LiuEphrem Wu
    • H04L12/28H04L12/56
    • H04L49/10
    • Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m.
    • 所描述的实施例提供了具有加速因子m的交叉开关中的分组交换的先入先出(FIFO)缓冲器。 FIFO缓冲器包括多个寄存器,其被配置为接收分组中的数据的N位部分和多个单端口存储器,每个存储器的宽度W分割成宽度W / S的S个部分。 第一逻辑模块耦合到寄存器和单端口存储器并且接收数据的N位部分和寄存器的输出。 耦合到单端口存储器的第二逻辑模块构造从单端口存储器读出的数据。 在时钟周期的顺序中,N位数据部分从第一逻辑模块交替地传送到单端口存储器的一段,并且对于每个时钟周期,第二逻辑模块以输出宽度构建数据输出数据包 基于m的加速因子。
    • 10. 发明申请
    • Buffered Crossbar Switch System
    • 缓冲交叉开关系统
    • US20100272117A1
    • 2010-10-28
    • US12430438
    • 2009-04-27
    • Ephrem WuTing ZhouSteven Pollack
    • Ephrem WuTing ZhouSteven Pollack
    • H04L12/56
    • H04L49/254H04L49/101H04L49/252H04L49/3027H04L49/3045H04L49/508H04Q3/0004H04Q2213/1302H04Q2213/1304H04Q2213/13076H04Q2213/13103H04Q2213/13322
    • Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an Ni-input by Mi-output switch fabric, wherein Ni and Mi are positive integers greater than one. Each crossbar switch includes an input buffer at each input node, a crosspoint buffer at each crosspoint of the switch fabric, and an output buffer at each output node. The input buffer has an arbiter that reads data packets from the input buffer according to a first scheduling algorithm. An arbiter reads data packets from a crosspoint buffer queue according to a second scheduling algorithm. The output node receives segments of data packets provided from one or more corresponding crosspoint buffers.
    • 描述的实施例提供数据模块之间的数据传输。 使用至少两个交叉开关,其中每个交叉开关的输入节点和输出节点耦合到对应的数据模块。 第i个交叉开关具有Mi输出开关结构的Ni输入,其中Ni和Mi是大于1的正整数。 每个交叉开关包括每个输入节点处的输入缓冲器,交换结构的每个交叉点处的交叉点缓冲器,以及每个输出节点处的输出缓冲器。 输入缓冲器具有根据第一调度算法从输入缓冲器读取数据分组的仲裁器。 仲裁器根据第二调度算法从交叉点缓冲队列读取数据包。 输出节点接收从一个或多个相应的交叉点缓冲器提供的数据分组段。