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1. 发明申请

US20130246875A1 Multi-Modal Signal Processing with Linearization 有权
标题翻译：多模态信号处理与线性化
公开(公告)号：US20130246875A1
公开(公告)日：2013-09-19
申请号：US13421328
申请日：2012-03-15
申请人： Timothy RYAN , Ravichandran Ramachandran
发明人： Timothy RYAN , Ravichandran Ramachandran
IPC分类号： G06F11/07
CPC分类号： H04L1/0026 , H04L1/203
摘要： A system for signal processing includes: a plurality of signal processing units associated with corresponding channels; a feedback channel for receiving a selected feedback signal through a selector of an output associated with each of the signal processing units; and a correlator connected to the feedback channel and having a receiving unit to receive the selected feedback signal, an error calculating unit to calculate an error based at least in part on the selected feedback signal, and a correction calculation unit to generate a correcting information based at least in part on the error. In some cases, the association between the signal processing units and the signal channels is configured based on a mode.
摘要翻译：一种用于信号处理的系统包括：与相应信道相关联的多个信号处理单元; 反馈通道，用于通过与每个信号处理单元相关联的输出的选择器接收所选择的反馈信号; 以及连接到所述反馈信道并具有接收单元以接收所选择的反馈信号的相关器，至少部分地基于所选择的反馈信号来计算误差的误差计算单元，以及基于所述反馈信号生成校正信息的校正计算单元至少部分是错误的。在一些情况下，信号处理单元和信号通道之间的关联是基于模式配置的。

2. 发明授权

US08739000B2 Multi-modal signal processing with linearization 有权
标题翻译：具有线性化的多模态信号处理
公开(公告)号：US08739000B2
公开(公告)日：2014-05-27
申请号：US13421328
申请日：2012-03-15
申请人： Timothy Ryan , Ravichandran Ramachandran
发明人： Timothy Ryan , Ravichandran Ramachandran
IPC分类号： H03M13/00 , G06F11/00 , G11B27/00
CPC分类号： H04L1/0026 , H04L1/203
摘要： A system for signal processing includes: a plurality of signal processing units associated with corresponding channels; a feedback channel for receiving a selected feedback signal through a selector of an output associated with each of the signal processing units; and a correlator connected to the feedback channel and having a receiving unit to receive the selected feedback signal, an error calculating unit to calculate an error based at least in part on the selected feedback signal, and a correction calculation unit to generate a correcting information based at least in part on the error. In some cases, the association between the signal processing units and the signal channels is configured based on a mode.
摘要翻译：一种用于信号处理的系统包括：与相应信道相关联的多个信号处理单元; 反馈通道，用于通过与每个信号处理单元相关联的输出的选择器接收所选择的反馈信号; 以及连接到所述反馈信道并具有接收单元以接收所选择的反馈信号的相关器，至少部分地基于所选择的反馈信号来计算误差的误差计算单元，以及基于所述反馈信号生成校正信息的校正计算单元至少部分是错误的。在一些情况下，信号处理单元和信号通道之间的关联是基于模式配置的。

3. 发明授权

US08600317B2 Linearization signal processing with context switching 失效
标题翻译：线性化信号处理与上下文切换
公开(公告)号：US08600317B2
公开(公告)日：2013-12-03
申请号：US13421354
申请日：2012-03-15
申请人： Timothy Ryan , Ravichandran Ramachandran
发明人： Timothy Ryan , Ravichandran Ramachandran
IPC分类号： H04B1/40
CPC分类号： H03F1/3247 , H03F3/24 , H04L27/368
摘要： A system for linearization signal processing with context switching comprises a plurality of signal processing units, a storage unit, a feedback channel, and a correlator. The plurality of signal processing units is associated with corresponding input data signals. The storage unit is to store context states associated with input data signals and corresponding feedback signals. The feedback channel is to convey feedback signals from outputs associated with the plurality of signal processing units. The correlator is coupled to the feedback channel and generates respective correcting information to be used by respective signal processing units, wherein a respective correcting information is based upon a context state and a feedback state associated with an input data signal.
摘要翻译：用于具有上下文切换的线性化信号处理的系统包括多个信号处理单元，存储单元，反馈信道和相关器。多个信号处理单元与相应的输入数据信号相关联。存储单元用于存储与输入数据信号和相应的反馈信号相关联的上下文状态。反馈信道用于传送与多个信号处理单元相关联的输出的反馈信号。相关器耦合到反馈信道并产生要由各个信号处理单元使用的相应校正信息，其中相应的校正信息基于与输入数据信号相关联的上下文状态和反馈状态。

4. 发明授权

US06345378B1 Synthesis shell generation and use in ASIC design 失效
标题翻译：综合壳生成与ASIC设计中的应用
公开(公告)号：US06345378B1
公开(公告)日：2002-02-05
申请号：US08409191
申请日：1995-03-23
申请人： Christian Joly , Zarir Sarkari , Ravichandran Ramachandran , Sarika Agrawal , Sanjay Adkar
发明人： Christian Joly , Zarir Sarkari , Ravichandran Ramachandran , Sarika Agrawal , Sanjay Adkar
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A practical approach for synthesis for million gate ASICs is based on the use of synthesis shells. The synthesis shell is generated by beginning with a gate level description of a fully characterized and optimized block. This gate level description is reduced by removing internal gates to produce a synthesis shell of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists and can be used for hierarchical synthesis in a customer's design environment, or as a deliverable from a provider of ASIC services in order to protect the intellectual property of such a provider. Since all the information that is needed by a synthesizer is available in the synthesis shell in netlist form, the shell is extremely accurate. The synthesis shell as mentioned above comprises a gate level description which is a subset of the synthesized block. This description is reduced by deleting elements of the gate level description according to a set of pre-specified criteria.
摘要翻译：用于百万门ASIC的实用方法是基于合成壳的使用。通过从完全表征和优化的块的门级描述开始生成合成shell。通过去除内部门来产生合成块的合成壳，来减少该门级描述。合成外壳保留块的输入负载和扇出，相对于块的时钟的输出延迟，对于与块的时钟相关的输入信号的建立/保持约束以及用于块的通过信号的从输入到输出的延迟。这样的合成外壳可以用作原始设计网表的替代品，可以用于客户设计环境中的层次化合成，也可以用于ASIC服务提供商的交付，以保护这种提供商的知识产权。由于合成器所需的所有信息都以网表形式在合成shell中可用，所以外壳非常准确。如上所述的合成壳包括作为合成块的子集的门级描述。通过根据一组预先指定的标准删除门级描述的元素来减少该描述。

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