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1. 发明授权

US07197625B1 Alignment and ordering of vector elements for single instruction multiple data processing 有权
标题翻译：用于单指令多数据处理的向量元素的对齐和排序
公开(公告)号：US07197625B1
公开(公告)日：2007-03-27
申请号：US09662832
申请日：2000-09-15
申请人： Timothy J. van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy J. van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F15/80 , G06F9/312
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30167 , G06F9/3885 , G06F9/3887
摘要： The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.
摘要翻译：本发明提供用于SIMD处理的向量元素的对准和排序。在用于SIMD处理的向量元素的对齐中，一个向量从存储器单元加载到第一寄存器中，另一个向量从存储器单元加载到第二寄存器中。第一个向量包含要生成的对齐向量的第一个字节。然后，确定指定对齐向量的第一个字节的起始字节。接下来，从第一寄存器提取向量，并且从第一寄存器的第一字节的第一位开始的第二寄存器继续通过第二寄存器中的位。最后，将所提取的矢量复制到第三寄存器中，使得第三寄存器包含对准用于SIMD处理的多个元素。在用于SIMD处理的向量元素的排序中，将第一向量从存储器单元加载到第一寄存器中，并且将第二向量从存储器单元加载到第二寄存器中。然后，从第一寄存器和第二寄存器中选择元件的子集。然后将来自子集的元素以适合于随后的SIMD向量处理的特定顺序复制到第三寄存器中的元素中。

2. 发明授权

US5933650A Alignment and ordering of vector elements for single instruction multiple data processing 失效
标题翻译：用于单指令多数据处理的向量元素的对齐和排序
公开(公告)号：US5933650A
公开(公告)日：1999-08-03
申请号：US947649
申请日：1997-10-09
申请人： Timothy J. van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy J. van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F5/00 , G06F7/76 , G06F9/30 , G06F9/315 , G06F15/80
CPC分类号： G06F7/76 , G06F5/00 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F2207/3828
摘要： The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.
摘要翻译：本发明提供用于SIMD处理的向量元素的对准和排序。在用于SIMD处理的向量元素的对齐中，一个向量从存储器单元加载到第一寄存器中，另一个向量从存储器单元加载到第二寄存器中。第一个向量包含要生成的对齐向量的第一个字节。然后，确定指定对齐向量的第一个字节的起始字节。接下来，从第一寄存器提取向量，并且从第一寄存器的第一字节的第一位开始的第二寄存器继续通过第二寄存器中的位。最后，将所提取的矢量复制到第三寄存器中，使得第三寄存器包含对准用于SIMD处理的多个元素。在用于SIMD处理的向量元素的排序中，将第一向量从存储器单元加载到第一寄存器中，并且将第二向量从存储器单元加载到第二寄存器中。然后，从第一寄存器和第二寄存器中选择元件的子集。然后将来自子集的元素以适合于随后的SIMD向量处理的特定顺序复制到第三寄存器中的元素中。

3. 发明授权

US08074058B2 Providing extended precision in SIMD vector arithmetic operations 有权
标题翻译：提供SIMD向量算术运算的扩展精度
公开(公告)号：US08074058B2
公开(公告)日：2011-12-06
申请号：US12480414
申请日：2009-06-08
申请人： Timothy J. Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy J. Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F15/8084
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行的结果元素写入累加器。然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

4. 发明授权

US07546443B2 Providing extended precision in SIMD vector arithmetic operations 有权
标题翻译：提供SIMD向量算术运算中的扩展精度
公开(公告)号：US07546443B2
公开(公告)日：2009-06-09
申请号：US11337440
申请日：2006-01-24
申请人： Timothy J. Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy J. Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F15/8084
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行的结果元素写入累加器。然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

5. 发明申请

US20090249039A1 Providing Extended Precision in SIMD Vector Arithmetic Operations 有权
标题翻译：在SIMD矢量算术运算中提供扩展精度
公开(公告)号：US20090249039A1
公开(公告)日：2009-10-01
申请号：US12480414
申请日：2009-06-08
申请人： Timothy Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy Van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F15/8084
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行的结果元素写入累加器。然后，将所得到的元素变换为N位元素，并写入第三寄存器以进一步操作或存储在存储器中。所得到的元件的变换可以包括例如舍入，夹紧和/或移动元件。

6. 发明授权

US5864703A Method for providing extended precision in SIMD vector arithmetic operations 失效
标题翻译：在SIMD向量算术运算中提供扩展精度的方法
公开(公告)号：US5864703A
公开(公告)日：1999-01-26
申请号：US947648
申请日：1997-10-09
申请人： Timothy van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F9/30 , G06F9/302 , G06F15/78 , G06F15/76
CPC分类号： G06F9/30014 , G06F15/8084 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一向量寄存器和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。然后，本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行结果写入累加器。然后，累加器中的每个元素被变换成N位元素并存储到存储器中。

7. 发明授权

US07159100B2 Method for providing extended precision in SIMD vector arithmetic operations 有权
标题翻译：在SIMD向量算术运算中提供扩展精度的方法
公开(公告)号：US07159100B2
公开(公告)日：2007-01-02
申请号：US09223046
申请日：1998-12-30
申请人： Timothy van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
发明人： Timothy van Hook , Peter Hsu , William A. Huffman , Henry P. Moreton , Earl A. Killian
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887 , G06F15/8084
摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.
摘要翻译：本发明在具有寄存器文件和累加器的处理器中提供SIMD算术运算的扩展精度。第一组数据元素和第二组数据元素分别被加载到第一向量寄存器和第二向量寄存器中。每个数据元素包括N位。接下来，从存储器中取出算术指令。算术指令被解码。然后，从寄存器文件读取第一向量寄存器和第二向量寄存器。然后，本发明对第一和第二向量寄存器中的相应数据元素执行算术指令。然后将执行结果写入累加器。然后，累加器中的每个元素被变换成N位元素并存储到存储器中。

8. 发明授权

US06859862B1 Method and apparatus for software management of on-chip cache 有权
标题翻译：片上缓存的软件管理方法和装置
公开(公告)号：US06859862B1
公开(公告)日：2005-02-22
申请号：US09545184
申请日：2000-04-07
申请人： Yu-Chung C. Liao , Peter A. Sandon , Howard Cheng , Peter Hsu
发明人： Yu-Chung C. Liao , Peter A. Sandon , Howard Cheng , Peter Hsu
IPC分类号： G06F12/08 , G06F9/30 , G06F12/12
CPC分类号： G06F9/30047 , G06F12/126
摘要： A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.
摘要翻译：一种微处理器，包括与所述控制单元连接的控制单元和高速缓存，用于存储要由所述控制使用的数据，其中所述高速缓存可选择性地配置为单个高速缓存或具有锁定的高速缓存部分和正常高速缓存部分的分区高速缓存。正常缓存部分由硬件实现的自动替换过程控制。锁定的高速缓存部分被锁定，使得自动替换进程不能修改锁定的高速缓存的内容。在指令集中提供指令，使得软件能够选择性地在锁定的高速缓存部分中分配线以对应于外部存储器中的位置，从而使锁定的高速缓存部分能够被软件完全地管理。

9. 发明申请

US20050038297A1 Synthesis and purification of 1,3,5-triamino-2,4,6-trinitrobenzene (TATB) 失效
标题翻译： 1,3,5-三氨基-2,4,6-三硝基苯（TATB）的合成与纯化
公开(公告)号：US20050038297A1
公开(公告)日：2005-02-17
申请号：US10910659
申请日：2004-08-02
申请人： Alexander Mitchell , Michael Coburn , Gregory Lee , Robert Schmidt , Philip Pagoria , Peter Hsu
发明人： Alexander Mitchell , Michael Coburn , Gregory Lee , Robert Schmidt , Philip Pagoria , Peter Hsu
IPC分类号： C06B21/00 , C06B25/04 , C07C211/52 , C07C29/32
CPC分类号： C06B25/04 , C06B21/0091 , C07C211/52
摘要： A method to convert surplus nitroarene explosives (picric acid, ammonium picrate,) into TATB is described. The process comprises three major steps: conversion of picric acid/ammonium picrate into picramide; conversion of picramide to TATB through vicarious nucleophilic substitution (VNS) of hydrogen chemistry; and purification of TATB.
摘要翻译：描述了将过量的硝基芳烃炸药（苦味酸，苦味酸铵）转化成TATB的方法。该方法包括三个主要步骤：将苦味酸/苦味酸铵转化成草甘膦; 通过氢化学的替代亲核取代（VNS）将picramide转化为TATB; 和TATB的纯化。

10. 发明申请

US20050030629A1 Optical layer system having antireflection properties 审中-公开
标题翻译：具有抗反射性能的光学层系
公开(公告)号：US20050030629A1
公开(公告)日：2005-02-10
申请号：US10903584
申请日：2004-08-02
申请人： Monika Kursawe , Edgar Boehm , Peter Hsu
发明人： Monika Kursawe , Edgar Boehm , Peter Hsu
IPC分类号： C03C17/34 , G02B1/10 , G02B1/11
CPC分类号： G02B1/116
摘要： The invention relates to an optical layer system having antireflection properties, where a layer package comprising a first layer having a refractive index in the range from 1.20 to 1.37 and a second, smooth layer having a refractive index of from 1.40 to 1.48 is located on at least one surface of a transparent, planar substrate, to a process for the production thereof, and to the use thereof.
摘要翻译：本发明涉及一种具有抗反射特性的光学层系统，其中包括折射率在1.20至1.37范围内的第一层和折射率为1.40至1.48的第二平滑层的层封装位于透明平面基材的至少一个表面，其制备方法及其用途。

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