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1. 发明申请

US20080080542A1 Architecture for downlink receiver bit rate processor 审中-公开
标题翻译：下行接收器比特率处理器的架构
公开(公告)号：US20080080542A1
公开(公告)日：2008-04-03
申请号：US11529148
申请日：2006-09-28
申请人： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
发明人： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
IPC分类号： H04L12/56
CPC分类号： H04B1/707 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0067
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

2. 发明申请

US20080080443A1 Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
标题翻译：无线下行接收机芯片速率处理与比特率处理之间的接口
公开(公告)号：US20080080443A1
公开(公告)日：2008-04-03
申请号：US11529146
申请日：2006-09-28
申请人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
发明人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
IPC分类号： H04B7/216
CPC分类号： H04B1/7105 , H04B2201/70707
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

3. 发明授权

US08358987B2 Re-quantization in downlink receiver bit rate processor 有权
标题翻译：在下行链路接收机比特率处理器中重新量化
公开(公告)号：US08358987B2
公开(公告)日：2013-01-22
申请号：US11529071
申请日：2006-09-28
申请人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
发明人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级并且提供编码的传输信道数据。后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

4. 发明申请

US20080080444A1 Transport channel buffer organization in downlink receiver bit rate processor 审中-公开
标题翻译：下行接收器比特率处理器中的传输信道缓冲器组织
公开(公告)号：US20080080444A1
公开(公告)日：2008-04-03
申请号：US11529182
申请日：2006-09-28
申请人： Timothy Fisher-Jeffes , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan
发明人： Timothy Fisher-Jeffes , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan
IPC分类号： H04B7/216
CPC分类号： H04L49/901 , H04L49/90
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

5. 发明授权

US08358988B2 Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
标题翻译：无线下行接收机芯片速率处理与比特率处理之间的接口
公开(公告)号：US08358988B2
公开(公告)日：2013-01-22
申请号：US11529146
申请日：2006-09-28
申请人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
发明人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/7105 , H04B2201/70707
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级并且提供编码的传输信道数据。后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

6. 发明申请

US20080081575A1 Re-Quantization in downlink receiver bit rate processor 有权
标题翻译：下行接收器比特率处理器中的重量化
公开(公告)号：US20080081575A1
公开(公告)日：2008-04-03
申请号：US11529071
申请日：2006-09-28
申请人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
发明人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

7. 发明授权

US08027371B2 Combine time multiplexed pilot (TMP) derotation with descrambling and despreading in data correlators used by rake receivers 有权
标题翻译：在耙式接收机使用的数据相关器中组合时分复用导频（TMP）解旋与解扰和解扩
公开(公告)号：US08027371B2
公开(公告)日：2011-09-27
申请号：US12103177
申请日：2008-04-15
申请人： Timothy Fisher-Jeffes , Dilip Muthukrishnan
发明人： Timothy Fisher-Jeffes , Dilip Muthukrishnan
IPC分类号： H04B1/00
CPC分类号： H04B1/7115 , H04B1/709 , H04B1/7117 , H04B2201/70701 , H04B2201/70707
摘要： The invention provides a code modification circuit for receiving a descrambling/dispreading code at a first input pair thereof and a pilot derotation code at a second input pair thereof, and arranged to combine the codes to form a combined code for providing to a correlator such that the correlator can recover data or a pilot signal from an input sequence supplied thereto.
摘要翻译：本发明提供了一种代码修改电路，用于在其第一输入对处接收解扰/解密码，并在其第二输入对处接收导频解码码，并且被布置成组合代码以形成用于提供给相关器的组合码，使得相关器可以从提供给它的输入序列中恢复数据或导频信号。

8. 发明授权

US07665010B2 Blind transport format detection for transmission link 有权
标题翻译：传输链路盲传输格式检测
公开(公告)号：US07665010B2
公开(公告)日：2010-02-16
申请号：US10515301
申请日：2003-05-20
申请人： Timothy Fisher-Jeffes , Jason Woodard
发明人： Timothy Fisher-Jeffes , Jason Woodard
IPC分类号： H03M13/03 , G06F7/02 , G01R31/28
CPC分类号： H04L1/0046 , H04L1/0054 , H04L1/0061
摘要： Receiver-side apparatus for a transmission link, the link using different transport formats for blocks of data, and using convolutional coding with additional error detection code information, for transmitting the blocks to the receiver side, the apparatus having a decoder for performing a trellis decode and tracebacks of one of the received coded blocks, to produce decoded data candidates, an error detection element for carrying out one or more speculative error detections on the candidates, assuming part of each candidate is the additional error detection code, and part is the block of data, and a format detector for determining a transport format based on a result of the speculative error detections, the apparatus being arranged to determine a probability of a candidate being valid, and prioritize carrying out the tracebacks or the speculative error detections according to the probabilities.
摘要翻译：用于传输链路的接收机侧装置，使用数据块的不同传输格式的链路，以及使用具有附加错误检测码信息的卷积编码，用于将块发送到接收机侧，该装置具有用于执行网格解码的解码器以及所接收的编码块之一的回溯以产生解码数据候选，用于对候选进行一个或多个推测性错误检测的错误检测元件，假设每个候选的一部分是附加错误检测码，并且部分是块以及格式检测器，用于基于所述推测性错误检测的结果确定传输格式，所述设备被配置为确定候选者有效的概率，并且根据所述方法优先执行所述回溯或推测性错误检测概率

9. 发明申请

US20080260009A1 Combine Time Multiplexed Pilot (TMP) Derotation with Descrambling and Despreading in Data Correlators Used by Rake Receivers 有权
标题翻译：在耙式接收器使用的数据相关器中进行解扰和解扩的组合时间复用导频（TMP）
公开(公告)号：US20080260009A1
公开(公告)日：2008-10-23
申请号：US12103177
申请日：2008-04-15
申请人： Timothy Fisher-Jeffes , Dilip Muthukrishnan
发明人： Timothy Fisher-Jeffes , Dilip Muthukrishnan
IPC分类号： H04B1/00
CPC分类号： H04B1/7115 , H04B1/709 , H04B1/7117 , H04B2201/70701 , H04B2201/70707
摘要： The invention provides a code modification circuit for receiving a descrambling/dispreading code at a first input pair thereof and a pilot derotation code at a second input pair thereof, and arranged to combine the codes to form a combined code for providing to a correlator such that the correlator can recover data or a pilot signal from an input sequence supplied thereto.
摘要翻译：本发明提供了一种代码修改电路，用于在其第一输入对处接收解扰/解密码，并在其第二输入对处接收导频解码码，并且被布置成组合代码以形成用于提供给相关器的组合码，使得相关器可以从提供给它的输入序列中恢复数据或导频信号。

10. 发明授权

US08125973B2 Time shared rake fingers and path searcher 有权
标题翻译：时间共享的耙子手指和路径搜索器
公开(公告)号：US08125973B2
公开(公告)日：2012-02-28
申请号：US12050999
申请日：2008-03-19
申请人： Timothy Fisher-Jeffes , Dilip Muthukrishnan , Thomas Keller
发明人： Timothy Fisher-Jeffes , Dilip Muthukrishnan , Thomas Keller
IPC分类号： H04J3/00 , H04B1/00
CPC分类号： H04B1/7117 , H04B2201/7071
摘要： A rake receiver having a rake receiver finger operated in a time multiplexed manner to perform the task a plurality of fingers, each of these fingers being a virtual finger allocated to a time slot in an operation cycle of the rake receiver finger, and wherein a buffer is provided for buffering at least one received chip of data, and where a spare virtual finger is provided such that any virtual finger may request extra processing within an operation cycle of the time multiplexed rake receiver finger.
摘要翻译：一种耙式接收机，具有以时间复用方式操作的耙机接收机手指，以执行多个手指，这些手指中的每一个是分配给耙机接收器手指的操作周期中的时隙的虚拟手指，并且其中缓冲器被提供用于缓冲至少一个接收的数据芯片，并且其中提供备用虚拟手指使得任何虚拟手指可以在时间复用耙机接收机手指的操作周期内请求额外的处理。

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