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    • 3. 发明授权
    • Logic level converter
    • 逻辑电平转换器
    • US4023050A
    • 1977-05-10
    • US684603
    • 1976-05-10
    • Jeffrey R. FoxWilliam D. Walsh
    • Jeffrey R. FoxWilliam D. Walsh
    • H03K3/356H03K17/0412H03K17/0416H03K19/0185H03K17/60H03K3/286H03K3/353H03K17/04
    • H03K17/04123H03K17/04163H03K19/018507H03K3/356008
    • A logic level converter converts an input signal having first and second voltage levels to an output signal having first and third voltage levels in which the voltage excursion of the output signal is greater than that of the input signal. The converter comprises first and second cross-coupled inverters in which the second inverter provides the output signal and is biased with respect to the first and third voltage levels and in which the first inverter is biased with respect to the third voltage level and the digital input signal. A voltage divider is associated with the first inverter to insure sufficient voltage swing for proper switching of the inverters. The inverters have dissimilar gains to insure that when the inverters are biased at equal voltages, the inverters always assume a predetermined state. The converter is implemented with PMOS field effect transistors and includes capacitors for increasing switching speed.
    • 逻辑电平转换器将具有第一和第二电压电平的输入信号转换为具有第一和第三电压电平的输出信号,其中输出信号的电压偏移大于输入信号的电压偏移。 该转换器包括第一和第二交叉耦合的反相器,其中第二反相器提供输出信号并且相对于第一和第三电压电平被偏置,并且其中第一反相器相对于第三电压电平被偏置,并且数字输入 信号。 一个分压器与第一个逆变器相关联,以确保足够的电压摆幅,以正确切换逆变器。 逆变器具有不同的增益,以确保当逆变器以相等的电压偏置时,逆变器总是采取预定状态。 该转换器由PMOS场效应晶体管实现,并且包括用于提高开关速度的电容器。