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1. 发明申请

US20130161694A1 THIN HETEREOSTRUCTURE CHANNEL DEVICE 有权
标题翻译：薄型结构通道设备
公开(公告)号：US20130161694A1
公开(公告)日：2013-06-27
申请号：US13607875
申请日：2012-09-10
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L29/78 , H01L27/12
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

2. 发明申请

US20130193492A1 SILICON CARBON FILM STRUCTURE AND METHOD 审中-公开
标题翻译：硅碳膜结构与方法
公开(公告)号：US20130193492A1
公开(公告)日：2013-08-01
申请号：US13360823
申请日：2012-01-30
申请人： THOMAS N. ADAM , Kangguo Cheng , Hong He , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
发明人： THOMAS N. ADAM , Kangguo Cheng , Hong He , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02447 , H01L21/02507 , H01L21/02529 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7848
摘要： An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.
摘要翻译：公开了一种改进的硅碳膜结构。膜结构包括多层硅碳和硅。多层形成具有增加的取代碳含量的应力膜结构，并且用于诱导改善某些类型的场效应晶体管的载流子迁移率的应力。

3. 发明授权

US09093260B2 Thin hetereostructure channel device 有权
标题翻译：薄型立体声通道装置
公开(公告)号：US09093260B2
公开(公告)日：2015-07-28
申请号：US13607875
申请日：2012-09-10
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/66 , H01L21/02 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L21/3065 , H01L29/10
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

4. 发明授权

US09087687B2 Thin heterostructure channel device 有权
标题翻译：薄异质结构通道器件
公开(公告)号：US09087687B2
公开(公告)日：2015-07-21
申请号：US13336251
申请日：2011-12-23
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/84 , H01L27/12 , H01L21/3065 , H01L29/10
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

5. 发明申请

US20130161693A1 THIN HETEREOSTRUCTURE CHANNEL DEVICE 有权
标题翻译：薄型结构通道设备
公开(公告)号：US20130161693A1
公开(公告)日：2013-06-27
申请号：US13336251
申请日：2011-12-23
申请人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Hong He , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/02057 , H01L21/02532 , H01L21/0262 , H01L21/3065 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/1054
摘要： A method of fabricating a semiconductor device that includes providing a substrate having at least a first semiconductor layer atop a dielectric layer, wherein the first semiconductor layer has a first thickness of less than 10 nm. The first semiconductor layer is etched with a a halide based gas at a temperature of less than 675° C. to a second thickness that is less than the first thickness. A second semiconductor layer is epitaxially formed on an etched surface of the first semiconductor layer. A gate structure is formed directly on the second semiconductor layer. A source region and a drain region is formed on opposing sides of the gate structure.
摘要翻译：一种制造半导体器件的方法，其包括提供在电介质层顶部具有至少第一半导体层的衬底，其中所述第一半导体层具有小于10nm的第一厚度。在小于675℃的温度下用卤化物基气体蚀刻第一半导体层至小于第一厚度的第二厚度。在第一半导体层的蚀刻表面上外延形成第二半导体层。栅极结构直接形成在第二半导体层上。源极区域和漏极区域形成在栅极结构的相对侧上。

6. 发明授权

US09190471B2 Semiconductor structure having a source and a drain with reverse facets 有权
标题翻译：具有反向刻面的源极和漏极的半导体结构
公开(公告)号：US09190471B2
公开(公告)日：2015-11-17
申请号：US13446350
申请日：2012-04-13
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Jinghong Li , Alexander Reznicek
IPC分类号： H01L29/76 , H01L21/336 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08 , H01L21/84
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/02579 , H01L21/02609 , H01L21/84 , H01L29/0657 , H01L29/0847 , H01L29/78
摘要： A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.
摘要翻译：包括半导体晶片的半导体结构。所述半导体晶片包括栅极结构，所述半导体晶片中与所述栅极结构的第一侧相邻的第一沟槽和与所述栅极结构的第二侧相邻的第二沟槽，所述第一和第二沟槽填充有掺杂的外延硅，在填充的第一沟槽中形成源极，并且在填充的第二沟槽中形成漏极，使得源极和漏极中的每一个凹入并具有倒置的面。在优选的示例性实施例中，外延硅掺杂有硼。

7. 发明授权

US08956938B2 Epitaxial semiconductor resistor with semiconductor structures on same substrate 有权
标题翻译：外延半导体电阻，半导体结构在同一基板上
公开(公告)号：US08956938B2
公开(公告)日：2015-02-17
申请号：US13472747
申请日：2012-05-16
申请人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
发明人： Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Thomas N. Adam
IPC分类号： H01L21/336 , H01L27/088
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/13 , H01L28/20 , H01L29/0649 , H01L29/36 , H01L29/41783
摘要： An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.
摘要翻译：提供了一种电气装置，其包括具有上半导体层，埋入介质层和基底半导体层的衬底。衬底中存在至少一个限定半导体器件区域和电阻器器件区域的隔离区域。半导体器件区域包括具有存在于基极半导体层中的背栅极结构的半导体器件。与背栅结构的电接触由穿过掩埋介电层的掺杂的外延半导体柱提供。外延半导体电阻存在于电阻器件区域中。从外延半导体电阻器延伸到基底半导体层的未掺杂的外延半导体柱提供了由外延半导体电阻器产生的用于散发到基极半导体层的热通路。未掺杂和掺杂的外延半导体柱由相同的外延半导体材料组成。

8. 发明授权

US08853750B2 FinFET with enhanced embedded stressor 有权
标题翻译： FinFET具有增强的嵌入式压力
公开(公告)号：US08853750B2
公开(公告)日：2014-10-07
申请号：US13457529
申请日：2012-04-27
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/36 , H01L29/7848 , H01L29/7851
摘要： A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region.
摘要翻译： finFET的沟道区域具有鳍片，鳍片具有平行于衬底表面的第一方向的顶点，每个鳍片从顶点向下延伸，栅极覆盖顶点和相邻鳍片之间。半导体应力区域至少沿着第一方向延伸离开翅片，以对通道区域施加应力。鳍状物FET的源极和漏极区域可以通过沟道区域彼此分离，源极和/或漏极至少部分地在半导体应力区域中。应力区域包括覆盖并从第一半导体区域延伸的第一半导体区域和第二半导体区域。第二半导体区域可以比第一半导体区域更重掺杂，并且第一和第二半导体区域可以具有相反的导电类型，其中第二半导体区域的至少一部分与第一半导体区域相交。

9. 发明授权

US08841188B2 Bulk finFET with controlled fin height and high-K liner 有权
标题翻译：散装finFET具有可控翅片高度和高K衬垫
公开(公告)号：US08841188B2
公开(公告)日：2014-09-23
申请号：US13604658
申请日：2012-09-06
申请人： Alexander Reznicek , Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz
发明人： Alexander Reznicek , Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823821 , H01L27/0924 , H01L29/0684 , H01L29/1054 , H01L29/66795
摘要： A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底上形成材料堆叠，所述材料堆叠包括在所述衬底上的第一介电层，所述第一电介质层上的第二电介质层和所述第二电介质层上的第三电介质层，其中所述第二电介质层是高k电介质。通过材料堆叠形成开口以暴露半导体衬底的表面。通过材料堆叠在开口中形成半导体材料。第一电介质层被选择性地去除到第二电介质层和半导体材料。栅极结构形成在半导体材料的沟道部分上。在一些实施例中，该方法可以提供多个finFET或者触发半导体器件，其中这些器件的鳍结构具有基本上相同的高度。

10. 发明授权

US08841185B2 High density bulk fin capacitor 有权
标题翻译：高密度散装散热片电容器
公开(公告)号：US08841185B2
公开(公告)日：2014-09-23
申请号：US13584176
申请日：2012-08-13
申请人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
发明人： Ali Khakifirooz , Thomas N. Adam , Kangguo Cheng , Alexander Reznicek
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L28/92 , H01L27/0805 , H01L29/785
摘要： A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finFETs by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density. Embodiments of the present invention include depletion-mode varactors and inversion-mode varactors.
摘要翻译：公开了一种高密度散装散热片电容器。通过进一步蚀刻散热片电容器以提供更多的表面积，从而在finFET附近形成翅片电容器，从而增加电容密度。本发明的实施例包括耗尽型变容二极管和反模式变容二极管。

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