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1. 发明授权

US07683413B2 Double sided container capacitor for a semiconductor device 有权
标题翻译：用于半导体器件的双面容器电容器
公开(公告)号：US07683413B2
公开(公告)日：2010-03-23
申请号：US11517045
申请日：2006-09-07
申请人： Thomas M. Graettinger , Marsela Pontoh , Thomas A. Figura
发明人： Thomas M. Graettinger , Marsela Pontoh , Thomas A. Figura
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.
摘要翻译：一种用于形成双面容器电容器的方法包括在电介质层的凹槽内形成第一电容器顶板层，然后在第一顶板层上形成第一单元电介质。接下来，在第一单元电介质层上形成第一和第二底板层，在第二底板层上形成第二单元电介质层。最后，在第二单元电介质层上形成第二顶板层，并且使用导电插塞或导电间隔件将第一和第二顶板层电连接。还描述了使用本发明方法形成的本发明的结构。

2. 发明授权

US07105403B2 Double sided container capacitor for a semiconductor device and method for forming same 有权
标题翻译：用于半导体器件的双面容器电容器及其形成方法
公开(公告)号：US07105403B2
公开(公告)日：2006-09-12
申请号：US10628994
申请日：2003-07-28
申请人： Thomas M. Graettinger , Marsela Pontoh , Thomas A. Figura
发明人： Thomas M. Graettinger , Marsela Pontoh , Thomas A. Figura
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a first cell dielectric on the first top plate layer. Next, first and second bottom plate layers are formed on the first cell dielectric layer, and a second cell dielectric layer is formed on the second bottom plate layers. Finally, a second top plate layer is formed on the second cell dielectric layer, and the first and second top plate layers are electrically connected using a conductive plug or conductive spacer. An inventive structure formed using the inventive method is also described.
摘要翻译：一种用于形成双面容器电容器的方法包括在电介质层的凹槽内形成第一电容器顶板层，然后在第一顶板层上形成第一单元电介质。接下来，在第一单元电介质层上形成第一和第二底板层，在第二底板层上形成第二单元电介质层。最后，在第二单元电介质层上形成第二顶板层，并且使用导电插塞或导电间隔件将第一和第二顶板层电连接。还描述了使用本发明方法形成的本发明的结构。

3. 发明授权

US09076888B2 Silicided recessed silicon 有权
公开(公告)号：US09076888B2
公开(公告)日：2015-07-07
申请号：US11614802
申请日：2006-12-21
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/8238 , H01L21/28 , H01L21/8234 , H01L27/108 , H01L29/49 , H01L29/66
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

4. 发明授权

US07019347B2 Dynamic random access memory circuitry comprising insulative collars 失效
标题翻译：包括绝缘套环的动态随机存取存储器电路
公开(公告)号：US07019347B2
公开(公告)日：2006-03-28
申请号：US11031478
申请日：2005-01-07
申请人： John M. Drynan , Thomas A. Figura
发明人： John M. Drynan , Thomas A. Figura
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76834 , H01L21/76885 , H01L23/485 , H01L27/10811 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , Y10T29/49124 , H01L2924/00
摘要： A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second different insulative material is deposited. The second insulative material is anisotropically etched effective to form a sidewall etch stop for the conductive structure. A third insulative material is deposited over the conductive structure and the sidewall etch stop. The third insulative material is different in composition from the second insulative material. A contact opening is etched through the third insulative material to the conductive structure using an etch chemistry which is substantially selective to the second insulative material of the sidewall etch stop. Integrated circuitry independent of the method of fabrication is disclosed.
摘要翻译：向导电结构形成导电接触的方法包括形成容纳在第一绝缘材料内并从第一绝缘材料向外突出的导电结构。存放第二种不同的绝缘材料。第二绝缘材料被各向异性蚀刻有效地形成用于导电结构的侧壁蚀刻停止。第三绝缘材料沉积在导电结构和侧壁蚀刻停止点上。第三绝缘材料的组成与第二绝缘材料不同。使用对侧壁蚀刻停止件的第二绝缘材料基本上选择性的蚀刻化学品，将接触开口通过第三绝缘材料蚀刻到导电结构。公开了与制造方法无关的集成电路。

5. 发明授权

US06664171B2 Method of alloying a semiconductor device 有权
公开(公告)号：US06664171B2
公开(公告)日：2003-12-16
申请号：US10304194
申请日：2002-11-25
申请人： Fernando Gonzalez , Thomas A. Figura , J. Brett Rolfson
发明人： Fernando Gonzalez , Thomas A. Figura , J. Brett Rolfson
IPC分类号： H01L21324
CPC分类号： H01L28/40 , H01L21/324 , H01L23/3171 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed in the substrate is hydrogen and optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be done after deposition of a metal layer, or at other process steps as desired.

6. 发明授权

US06596648B2 Material removal method for forming a structure 有权
公开(公告)号：US06596648B2
公开(公告)日：2003-07-22
申请号：US10193850
申请日：2002-07-11
申请人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
发明人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
IPC分类号： H01L2100
CPC分类号： H01L27/10852 , H01L21/2815 , H01L21/28525 , H01L21/30608 , H01L21/32134 , H01L21/76232 , H01L21/76237 , H01L21/7624 , H01L21/76838 , H01L21/76897 , H01L27/10817 , H01L28/60 , H01L29/66492 , H01L29/66575
摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

7. 发明授权

US06507065B2 Doped silicon structure with impression image on opposing roughened surfaces 失效
标题翻译：在相对的粗糙表面上具有印模图像的掺杂硅结构
公开(公告)号：US06507065B2
公开(公告)日：2003-01-14
申请号：US09897258
申请日：2001-07-02
申请人： Thomas A. Figura , Zhiquiang Wu , Li Li
发明人： Thomas A. Figura , Zhiquiang Wu , Li Li
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , Y10S438/964
摘要： A silicon structure is formed that includes a free-standing wall having opposing roughen ed inner and outer surfaces using ion implantation and an unplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughen ed by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughen ed outer surface to which has been transferred a near-impression image topography of the opposing inner surface.
摘要翻译：形成硅结构，其包括使用离子注入的具有相对粗糙的内表面和外表面的独立壁和对植入硅有选择性的未用硅蚀刻工艺。通常，该方法在其中形成多晶硅层的绝缘材料层中提供凹部。随后在多晶硅层上形成一层HSG或CSG多晶硅，然后将离子注入HSG或CSG多晶硅层以及下层多晶硅层。然后进行上述选择性蚀刻工艺，导致相对未被注入的部分被蚀刻掉，并且高度注入的部分被静置以形成自立壁。独立式墙体的内表面由HSG或CSG多晶硅层粗糙化。独立的墙壁还具有粗糙的外表面，已经转移到相对的内表面的近印象图像形貌。

8. 发明授权

US06373084B1 Shared length cell for improved capacitance 有权
公开(公告)号：US06373084B1
公开(公告)日：2002-04-16
申请号：US09729848
申请日：2000-12-06
申请人： Thomas A. Figura
发明人： Thomas A. Figura
IPC分类号： H01L27108
摘要： A container capacitor having an elongated storage electrode for enhanced capacitance in a dynamic random access memory circuit. The electrode is preferably twice the length of the typical cell and may be coated with hemispherical-grain polysilicon to further increase the surface area of the electrode.

9. 发明授权

US06355536B1 Selective method to form roughened silicon 失效
公开(公告)号：US06355536B1
公开(公告)日：2002-03-12
申请号：US09093217
申请日：1998-06-08
申请人： Thomas A. Figura , Zhigiang Wu , Li Li
发明人： Thomas A. Figura , Zhigiang Wu , Li Li
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L28/91
摘要： A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.

10. 发明授权

US06225208B1 Method and structure for improved alignment tolerance in multiple, singularized plugs 有权
标题翻译：用于改善多个单个插头中的对准公差的方法和结构
公开(公告)号：US06225208B1
公开(公告)日：2001-05-01
申请号：US09576503
申请日：2000-05-23
申请人： Thomas A. Figura
发明人： Thomas A. Figura
IPC分类号： H01L214763
CPC分类号： H01L21/768 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.
摘要翻译：提供了一种改进的方法和结构，其增加了多个奇异插头中的对准公差。本发明公开了一种用于形成具有增加的表面积的单个插头触点的新颖方法，用于改善半导体层之间的对准。此外，改进的插头触头特别适合于接收对它们具有任何锥度的接触结构。 IGFETS和由该设计形成的其它器件可以用于各种有益的应用，例如，逻辑或记忆

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