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1. 发明授权

US6094436A Integrated multiport switch having shared media access control circuitry 失效
标题翻译：具有共享媒体访问控制电路的集成多端口交换机
公开(公告)号：US6094436A
公开(公告)日：2000-07-25
申请号：US992921
申请日：1997-12-18
申请人： Thomas J. Runaldue , Somnath Viswanath , Peter Ka-Fai Chow
发明人： Thomas J. Runaldue , Somnath Viswanath , Peter Ka-Fai Chow
IPC分类号： G06F5/06 , G06F12/12 , G11C7/10 , G11C11/412 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L29/06 , H04Q3/545 , H04B7/212
CPC分类号： H04L41/0213 , G06F12/128 , G06F5/06 , G11C11/412 , G11C7/1015 , H04L49/3054 , H04L69/26 , H04Q3/54591 , H04L49/103 , H04L49/30 , H04L49/351 , H04L49/354 , H04Q2213/1316 , H04Q2213/13162
摘要： An integrated multiport switch (IMS) in which one combinational logic and register arrangement is provided for executing similar media access control (MAC) functions for a plurality of switch ports. The current access state at each of a plurality of switch ports is maintained at a single state storage location, whereby access of a stored port MAC state and update thereof is simplified. Access to state storage in coordination with the single common combinational logic and register arrangement enables MAC functions for each of the plurality of ports to be performed on a time shared basis to maximize efficiency of use of chip resources and architecture space.
摘要翻译：一种集成多端口交换机（IMS），其中提供一个组合逻辑和寄存器装置，用于为多个交换机端口执行类似的媒体访问控制（MAC）功能。在多个交换机端口中的每一个处的当前访问状态被保持在单个状态存储位置，由此简化了存储的端口MAC状态的访问及其更新。与单个公共组合逻辑和寄存器布置协调地访问状态存储使得能够以时间共享的方式执行多个端口中的每一个的MAC功能，以最大化芯片资源和架构空间的使用效率。

2. 发明授权

US6084878A External rules checker interface 失效
标题翻译：外部规则检查器界面
公开(公告)号：US6084878A
公开(公告)日：2000-07-04
申请号：US993715
申请日：1997-12-18
申请人： Ian Crayford , Denise Kerstein , Peter Ka-Fai Chow , Chandan Egbert , Thomas J. Runaldue
发明人： Ian Crayford , Denise Kerstein , Peter Ka-Fai Chow , Chandan Egbert , Thomas J. Runaldue
IPC分类号： H04L12/46 , H04L12/56 , H04L12/28 , H04L12/54
CPC分类号： H04L12/4641 , H04L49/25 , H04L49/3027 , H04L49/351 , H04L49/354
摘要： An interface located on a network switch transmits header information to an external device that makes data forwarding decisions. The interface receives and transmits header information that includes the source and destination address of the data. The external device generates data forwarding information and transmits the information back to the switch via the interface device. The network switch uses the information obtained via the interface and forwards the data packets to the appropriate destination.
摘要翻译：位于网络交换机上的接口将报头信息发送到进行数据转发决策的外部设备。该接口接收并发送包括数据的源地址和目标地址的标题信息。外部设备生成数据转发信息，并通过接口设备将信息发送回交换机。网络交换机使用通过接口获得的信息，并将数据包转发到适当的目的地。

3. 发明授权

US06393021B1 Integrated multiport switch having shared data receive FIFO structure 失效
标题翻译：具有共享数据接收FIFO结构的集成多端口开关
公开(公告)号：US06393021B1
公开(公告)日：2002-05-21
申请号：US08992815
申请日：1997-12-18
申请人： Peter Ka-Fai Chow , Thomas J. Runaldue
发明人： Peter Ka-Fai Chow , Thomas J. Runaldue
IPC分类号： H04Q1100
CPC分类号： H04L49/3009 , G06F13/1605 , G06F13/24 , G11C11/412 , H04L12/1863 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L41/0213 , H04L47/50 , H04L47/6225 , H04L49/103 , H04L49/201 , H04L49/25 , H04L49/255 , H04L49/30 , H04L49/3027 , H04L49/3054 , H04L49/351 , H04L49/354 , H04L49/40 , H04L49/50 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9063 , H04L49/9073 , H04L49/9078 , H04L49/9084 , H04Q3/54591 , H04Q2213/1316 , H04Q2213/13162
摘要： An integrated multiport switch (IMS) having a receive FIFO structure with a single port RAM, for storing network communication data received from each port of the switch. The RAM is connected to a FIFO control unit, which is coupled to a MAC for each port by a MAC bus, by a FIFO memory input bus. Writing of data received from each port via the MAC bus to the RAM is controlled on a time shared basis. The FIFO control unit includes a receive RAM interface that is connected to the MAC bus for receiving communication data from the ports and to the FIFO memory input bus for transferring communication data to the RAM for temporary storage. As the FIFO memory input bus has a larger bit transfer capacity than the MAC bus, the receive RAM interface can accumulate incoming data during clock cycles in which data is being read from the single port RAM. When the accumulated data for a given port is to be written to the RAM in a subsequent write cycle, it is then combined with additional incoming data for the same port received at that time for transfer to the RAM.
摘要翻译：具有具有单端口RAM的接收FIFO结构的集成多端口交换机（IMS），用于存储从交换机的每个端口接收的网络通信数据。 RAM连接到FIFO控制单元，FIFO控制单元通过FIFO存储器输入总线通过MAC总线与每个端口的MAC耦合。通过MAC总线将从每个端口接收到的数据写入RAM是以时间共享为基础进行控制的。 FIFO控制单元包括接收RAM接口，该接口连接到MAC总线，用于接收来自端口的通信数据和FIFO存储器输入总线，用于将通信数据传送到RAM用于临时存储。由于FIFO存储器输入总线具有比MAC总线更大的位传输容量，所以接收RAM接口可以在从单端口RAM读取数据的时钟周期期间累加输入数据。当给定端口的累加数据在随后的写周期中被写入RAM时，然后将其与用于传送到RAM的同一端口的附加输入数据组合。

4. 发明授权

US06169742A Multiport data network switch having direct media access control link to external management 失效
标题翻译：多端口数据网络交换机具有直接的媒体访问控制链接到外部管理
公开(公告)号：US06169742A
公开(公告)日：2001-01-02
申请号：US08992923
申请日：1997-12-18
申请人： Peter Ka-Fai Chow , Thomas J. Runaldue
发明人： Peter Ka-Fai Chow , Thomas J. Runaldue
IPC分类号： H04L1256
CPC分类号： H04L49/3009 , G06F13/1605 , G06F13/24 , G11C11/412 , H04L12/1863 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L41/0213 , H04L47/50 , H04L47/6225 , H04L49/103 , H04L49/201 , H04L49/25 , H04L49/255 , H04L49/30 , H04L49/3027 , H04L49/3054 , H04L49/351 , H04L49/354 , H04L49/40 , H04L49/50 , H04L49/552 , H04L49/555 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9063 , H04L49/9073 , H04L49/9078 , H04L49/9084 , H04Q3/54591 , H04Q2213/1316 , H04Q2213/13162
摘要： An integrated multiport switch (IMS) for a data network has a management port for direct communication with an external management agent. The switch, which is integrated into a single chip, includes a management interface that comprises logic circuit elements. This interface acts as a virtual physical layer for both the media access controller (MAC) at the management port and the MAC at the external management agent. The latter may be located on the same circuit board as the IMS chip. PHY devices for these MACs are eliminated while the collision signal and carrier sense signal generation functions are maintained. The PHY devices are replaced by a logic interface while permitting use of the standard Simplified Network Management Protocol (SNMP) software for the interfacing operations. No modification of MAC software is required.
摘要翻译：用于数据网络的集成多端口交换机（IMS）具有用于与外部管理代理进行直接通信的管理端口。集成到单个芯片中的开关包括包括逻辑电路元件的管理接口。该接口充当管理端口的媒体访问控制器（MAC）和外部管理代理的MAC的虚拟物理层。后者可以位于与IMS芯片相同的电路板上。消除了用于这些MAC的PHY设备，同时保持了冲突信号和载波感测信号生成功能。 PHY设备被逻辑接口替代，同时允许使用标准简化网络管理协议（SNMP）软件进行接口操作。不需要修改MAC软件。

5. 发明授权

US06141350A Auto-negotiation using negative link pulses 有权
标题翻译：使用负链路脉冲进行自动协商
公开(公告)号：US06141350A
公开(公告)日：2000-10-31
申请号：US291036
申请日：1999-04-14
申请人： Dinesh Mahale , Thomas J. Runaldue
发明人： Dinesh Mahale , Thomas J. Runaldue
IPC分类号： H04J3/06 , H04L5/14 , H04L12/24 , H04L12/413 , H04L25/03 , H04L29/06 , H04L29/08 , H04L12/40 , H04J3/02
CPC分类号： H04L25/03885 , H04J3/0688 , H04L12/40032 , H04L12/413 , H04L41/046 , H04L5/1438 , H04L69/323 , H04L49/3054
摘要： A novel auto-negotiation system capable of performing auto-negotiation using negative link pulses. The auto-negotiation system operates in a network transceiver for interconnecting multiple hub communication devices having different operating speeds and link partners provided on a transmission medium. The network transceiver comprises physical layer devices for supporting data exchange between the hub devices and the link partners, and an auto-negotiation device that transmits and receives link pulses of a prescribed polarity carrying auto-negotiation information to and from the link partners to select a mode of communication between the hub devices and the link partners. A reverse polarity detection and correction circuit is provided for supporting auto-negotiation operations when link pulses received from a link partner have a reverse polarity. In a preferred embodiment, the reverse polarity detection and correction circuit comprises a polarity detector for detecting polarity of the link pulses received from the link partner, and a link pulse detector for distinguishing link pulses from data received from the link partner. A polarity reversing circuit responsive to the polarity detector and the link pulse detector reverses polarity of the received link pulses.
摘要翻译：一种能够使用负链路脉冲执行自动协商的新型自动协商系统。自动协商系统在网络收发器中操作，用于互连具有不同操作速度的多个集线器通信设备和设置在传输介质上的链路伙伴。网络收发器包括用于支持集线器设备和链路伙伴之间的数据交换的物理层设备，以及自动协商设备，该设备向链路伙伴发送和接收带有自动协商信息的规定极性的链路脉冲，以选择一个集线器设备和链路伙伴之间的通信模式。提供了反向极性检测和校正电路，用于在从链路伙伴接收到的链路脉冲具有相反极性时支持自动协商操作。在优选实施例中，反极性检测和校正电路包括用于检测从链路伙伴接收的链路脉冲的极性的极性检测器和用于区分链路脉冲与从链路伙伴接收的数据的链路脉冲检测器。响应于极性检测器和链路脉冲检测器的极性反转电路反转所接收的链路脉冲的极性。

6. 发明授权

US6115389A Auto-negotiation for multiple ports using shared logic 失效
标题翻译：使用共享逻辑自动协商多个端口
公开(公告)号：US6115389A
公开(公告)日：2000-09-05
申请号：US291030
申请日：1999-04-14
申请人： Dinesh Mahale , Thomas J. Runaldue
发明人： Dinesh Mahale , Thomas J. Runaldue
IPC分类号： G01B7/02 , G01R31/08 , H04B3/46 , H04J3/06 , H04L5/14 , H04L12/24 , H04L12/413 , H04L12/46 , H04L25/03 , H04L29/06 , H04L29/08 , H04B7/212 , H04L12/43
CPC分类号： H04L25/03885 , G01B7/02 , H04B3/46 , H04J3/0688 , H04L12/40032 , H04L12/413 , H04L12/4625 , H04L41/046 , H04L5/1438 , H04L69/18 , H04L69/323 , G01R31/086 , H04L49/3054
摘要： A data communication device having multiple ports is provided with an auto-negotiation system for performing auto-negotiation with multiple link partners connected to the ports. The auto-negotiation system has a memory and an auto-negotiation unit including transmit, receive and arbitration state machines for performing transmit, receive and arbitration state diagrams compliant with the IEEE 802.3 Standard. The auto-negotiation unit operates in a time-division multiplexing mode using successive time slots for supporting auto-negotiation operations for different ports. The memory is used for storing state diagram variables for a port in a time interval between the time slots assigned to that port.
摘要翻译：具有多个端口的数据通信设备设置有用于与连接到端口的多个链路伙伴进行自动协商的自动协商系统。自动协商系统具有存储器和自动协商单元，包括用于执行符合IEEE 802.3标准的发送，接收和仲裁状态图的发送，接收和仲裁状态机。自动协商单元使用连续时隙以时分多路复用方式工作，以支持不同端口的自动协商操作。内存用于在分配给该端口的时隙之间的时间间隔内存储端口的状态图变量。

7. 发明授权

US5835719A Apparatus and method for remote wake-up in system having interlinked networks 失效
标题翻译：具有互连网络的系统中用于远程唤醒的装置和方法
公开(公告)号：US5835719A
公开(公告)日：1998-11-10
申请号：US972093
申请日：1997-11-17
申请人： Glen Gibson , Thomas J. Runaldue , Ching Yu
发明人： Glen Gibson , Thomas J. Runaldue , Ching Yu
IPC分类号： G06F1/32 , H04L12/12 , G06F13/38
CPC分类号： G06F1/3209 , H04L12/12 , Y02B60/32 , Y02B60/34
摘要： An apparatus and method for remote wake-up of an intended node within a data exchange system having interlinked networks (e.g., router-interlinked LAN's) is disclosed. A wake-up commanding format is disclosed wherein a sequence corresponding to the address of the intended node is embedded N consecutive times (e.g., at least 16 consecutive times) extensively through the respective data fields of one or more packets sent from a remote source node to the intended node. When this particular sequence is received by the intended node while the intended node is in a sleep mode, a wake-up operation is responsively initiated so that the sleeping node will awaken, at least for a time, to respond to future received packets.
摘要翻译：公开了一种用于在具有互连网络（例如，路由器互连LAN）的数据交换系统内远程唤醒预期节点的装置和方法。公开了一种唤醒命令格式，其中对应于预期节点的地址的序列通过从远程源节点发送的一个或多个分组的相应数据字段被广泛地连续N次（例如，至少16个连续时间）到目标节点。当预期节点处于睡眠模式时，当预定节点接收到该特定序列时，响应地启动唤醒操作，使得休眠节点至少在一段时间内唤醒以响应未来接收到的分组。

8. 发明授权

US06175902B1 Method and apparatus for maintaining a time order by physical ordering in a memory 失效
标题翻译：用于通过存储器中的物理排序来维持时间顺序的方法和装置
公开(公告)号：US06175902B1
公开(公告)日：2001-01-16
申请号：US08992925
申请日：1997-12-18
申请人： Thomas J. Runaldue , Bahadir Erimli
发明人： Thomas J. Runaldue , Bahadir Erimli
IPC分类号： G06F1200
CPC分类号： H04L49/901 , G06F12/128 , G11C7/1015 , H04L41/0213 , H04L49/201 , H04L49/90 , H04L49/9084 , H04Q3/54591
摘要： A method and arrangement for maintaining a time order of entries in a memory determines a row in which the entry will be stored, the memory being logically divided into rows and columns. The columns are arranged sequentially in each row from the newest to the oldest. Once the row in which the entry will be stored is determined, the entry is stored in that row in the column (or entry location) that is the newest column. The entry that was previously in the newest column is shifted to the next older column, and the entry that was previously in the next older column is shifted to the next most older column, etc. If a row is completely filled prior to the writing of a new entry, then the entry in the oldest column is removed from the memory and the other entries shifted.
摘要翻译：用于维护存储器中条目的时间顺序的方法和装置确定了将存储该条目的行，该存储器在逻辑上被划分成行和列。这些列按照从最新到最旧的顺序排列。一旦确定了条目将被存储的行，条目将被存储在作为最新列的列（或入口位置）中的该行中。先前在最新列中的条目将转移到下一个较旧的列，并且先前在下一个较旧列中的条目将转移到下一个较旧的列等。如果在写入之前完整填写了一行一个新条目，则最旧列中的条目将从内存中删除，其他条目移动。

9. 发明授权

US5672993A CMOS current mirror 失效
标题翻译： CMOS电流镜
公开(公告)号：US5672993A
公开(公告)日：1997-09-30
申请号：US601898
申请日：1996-02-15
申请人： Thomas J. Runaldue
发明人： Thomas J. Runaldue
IPC分类号： G05F3/26 , H03K17/62
CPC分类号： G05F3/262
摘要： A current mirror circuit for mirroring current in CMOS integrated circuit technology includes a current mirror arrangement formed of first and second P-channel MOS transistors (MP32,MP33), a variable input current source (I.sub.CS), a first source follower transistor (MN34), a second source follower transistor (MP35), a current-sinking transistor (MN31), and a load circuit 212. The load circuit is formed of a load transistor (MN36) and a load resistor (R1). In an alternate embodiment, the load circuit is formed of a single load resistor. As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).
摘要翻译：用于在CMOS集成电路技术中镜像电流的电流镜电路包括由第一和第二P沟道MOS晶体管（MP32，MP33），可变输入电流源（ICS），第一源极跟随器晶体管（MN34），第二源极跟随器晶体管（MP35），电流吸收晶体管（MN31）和负载电路212.负载电路由负载晶体管（MN36）和负载电阻（R1）构成。在替代实施例中，负载电路由单个负载电阻器形成。结果，注入第一P沟道MOS晶体管（MP32）的电流量更精确地镜像到第二P沟道MOS晶体管（MP33）中。

10. 发明授权

US5191244A N-channel pull-up transistor with reduced body effect 失效
标题翻译：具有减少身体效应的N沟道拉杆晶体管
公开(公告)号：US5191244A
公开(公告)日：1993-03-02
申请号：US760313
申请日：1991-09-16
申请人： Thomas J. Runaldue , Qazi R. M. Mahmood
发明人： Thomas J. Runaldue , Qazi R. M. Mahmood
IPC分类号： H01L21/8238 , H01L27/088 , H01L27/092 , H03K17/041 , H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/094 , H03K19/0952
CPC分类号： H03K17/04106 , H01L27/088 , H03K17/162 , H03K19/00315 , H03K19/00361 , H03K2217/0018
摘要： A CMOS output buffer circuit employing an N-channel pull-up transistor with reduced body effect includes an N-channel pull-up transistor (N2), an N-channel coupling transistor (N1), and an N-channel discharging transistor (N3). The pull-up transistor has its drain connected to an upper power supply potential (VCC), its source connected to an output node (20), its gate connected to a first internal node (B), and its local substrate connected to a second internal node (A). The coupling transistor has its source connected to the second internal node (A), its drain connected to the source of the pull-up transistor, its gate connected to the first internal node (B), and its local substrate connected to the local substrate of the pull-up transitor (N2). The discharging transistor has its drain connected to the second internal node (A), its source connected to a lower power supply potential (VCC), its gate connected to a third internal node (C), and its local substrate connected to the lower power supply potential (VSS). The coupling transistor and the discharging transistor serve to reduce the body effect on the pull-up transistor (N2) and to provide higher immunity from noise on the upper power supply potential (VCC).
摘要翻译：采用具有减小的体效应的N沟道上拉晶体管的CMOS输出缓冲电路包括N沟道上拉晶体管（N2），N沟道耦合晶体管（N1）和N沟道放电晶体管（N3 ）。上拉晶体管的漏极连接到上电源电位（VCC），其源极连接到输出节点（20），其栅极连接到第一内部节点（B），并且其栅极连接到第二内部节点内部节点（A）。耦合晶体管的源极连接到第二内部节点（A），其漏极连接到上拉晶体管的源极，其栅极连接到第一内部节点（B），其局部衬底连接到局部衬底的上拉电阻（N2）。放电晶体管的漏极连接到第二内部节点（A），其源极连接到较低的电源电位（VCC），其栅极连接到第三个内部节点（C），其局部衬底连接到较低功率电源（VSS）。耦合晶体管和放电晶体管用于减小上拉晶体管（N2）的体效应，并提供较高的上电源电压（VCC）上的噪声抗扰度。

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