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    • 8. 发明授权
    • Method for testing transducer horn Assembly used in debubbling by
monitoring operating frequency
    • 测量传感器喇叭的方法通过监测工作频率来进行脱泡时使用的组件
    • US6109092A
    • 2000-08-29
    • US477926
    • 2000-01-05
    • Robert Peter Kraus, Jr.Fugui HeRoland J. KoestnerSteven D. PossanzaPaul P. Zontek
    • Robert Peter Kraus, Jr.Fugui HeRoland J. KoestnerSteven D. PossanzaPaul P. Zontek
    • G01N27/02B01D19/00G01H3/00G01H13/00G01H15/00G01M19/00
    • G01H13/00B01D19/0078G01H15/00G01H3/005Y10S261/19
    • A method and apparatus for evaluating the end cap round transducer horn assemblies used in debubbling operations wherein the ECR THA can be evaluated off-line at both high and low power and on-line by making electrical measurements on the ECR THA. The electrical measurements are used to characterize the physical condition of the piezoelectric ceramics of the THA. A test box is employed to practice the method. The test box is connected between the THA and a signal analyzer. Power is supplied to the THA and the electrical signals across the THA are sampled. The sampled electrical signals are transmitted to the signal analyzer while maintaining the amplitude and phase relationship thereof. The sampled electrical signals are used to generate an impedance trace for the particular THA. That impedance trace is compared to a model impedance trace. In such manner, it can be determined whether the ECR THA is operational. Further, if the ECR THA is in working condition, the impedance trace can be used to determine how efficiently it is operating. This allows for an ultimate determination to be made of how well a particular ECR THA is functioning.
    • 一种用于评估在脱泡操作中使用的端盖圆形传感器喇叭组件的方法和装置,其中ECR THA可以通过对ECR THA进行电气测量而在高功率和低功率下在线评估。 电气测量用于表征THA的压电陶瓷的物理状态。 使用测试箱来实施该方法。 测试箱连接在THA和信号分析仪之间。 电源被提供给THA,并且跨越THA的电信号被采样。 将采样的电信号传送到信号分析器,同时保持其幅度和相位关系。 采样的电信号用于产生特定THA的阻抗迹线。 该阻抗曲线与模型阻抗曲线进行比较。 以这种方式,可以确定ECR THA是否可操作。 此外,如果ECR THA处于工作状态,阻抗迹线可用于确定其工作效率。 这允许最终确定特定ECR THA的功能如何。
    • 9. 发明授权
    • Method of making a HgCdTe thin film transistor
    • 制造HgCdTe薄膜晶体管的方法
    • US5403760A
    • 1995-04-04
    • US151722
    • 1993-11-15
    • Richard A. SchiebelMichael A. KinchRoland J. Koestner
    • Richard A. SchiebelMichael A. KinchRoland J. Koestner
    • H01L21/34H01L21/265
    • H01L29/66969Y10S148/064Y10S148/139
    • Group II-VI thin film transistors, a method of making same and a monolithic device containing a detector array as well as transistors coupled thereto wherein, according to a first embodiment, there is provided a group II-VI insulating substrate, a doped layer of a group II-VI semiconductor material disposed over the substrate, an insulating gate region disposed over the doped layer, a pair of spaced contacts on the doped layer providing source and drain contacts, a gate contact disposed over the insulating gate region, an insulating layer disposed over exposed regions of the substrate, doped layer, insulating gate region and contacts and metallization disposed on the insulating layer and extending through the insulating layer to the contacts. The thickness of the doped layer is less than the maximum depletion region thickness thereof. In accordance with a second embodiment, there is provided a group II-VI insulating substrate, a first conductive doped group II-VI semiconductor layer disposed over the substrate, a second doped group II-VI layer disposed over the first layer and forming a Schottky barrier therewith, an insulating layer disposed over exposed regions of the substrate, first doped layer and second doped layer and metallization disposed on the insulating layer and extending through the insulating layer to spaced regions on the first layer to form source and drain contacts thereto and to the second layer to form a gate contact thereto. The thickness of said first layer is less than the maximum depth of the depletion region formed by the junction of the first and second layers.
    • II-VI族薄膜晶体管,其制造方法和包含检测器阵列的单片器件以及耦合到其上的晶体管,其中根据第一实施例,提供了II-VI族绝缘衬底,掺杂层 设置在所述衬底上的II-VI族半导体材料,设置在所述掺杂层上的绝缘栅极区,在所述掺杂层上提供源极和漏极触点的一对隔开的触点,设置在所述绝缘栅极区上方的栅极触点,绝缘层 设置在衬底的暴露区域,掺杂层,绝缘栅极区域和布置在绝缘层上并且穿过绝缘层延伸到触点的触点和金属化。 掺杂层的厚度小于其最大耗尽区厚度。 根据第二实施例,提供了一种组II-VI绝缘衬底,设置在衬底上的第一导电掺杂组II-VI半导体层,设置在第一层上并形成肖特基的第二掺杂组II-VI层 设置在衬底的暴露区域上的绝缘层,第一掺杂层和第二掺杂层以及设置在绝缘层上的金属化层,并延伸穿过绝缘层到第一层上的间隔的区域,以形成源极和漏极触点,并且 第二层与其形成栅极接触。 所述第一层的厚度小于由第一层和第二层的接合形成的耗尽区的最大深度。