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1. 发明申请

US20080229128A1 System and Computer Program Product for Dynamically Managing Power in MicroProcessor Chips According to Present Processing Demands 有权
标题翻译：根据当前处理要求，微处理器芯片动态管理系统和计算机程序产品
公开(公告)号：US20080229128A1
公开(公告)日：2008-09-18
申请号：US12131507
申请日：2008-06-02
申请人： Thomas J. Heller , Michael Ignatowski , Bernard Steele Meyerson , James Walter Rymarczyk
发明人： Thomas J. Heller , Michael Ignatowski , Bernard Steele Meyerson , James Walter Rymarczyk
IPC分类号： G06F1/00
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。选择执行一个进程。然后识别执行该过程所需的硬件元素。微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。

2. 发明申请

US20080059769A1 MULTIPLE-CORE PROCESSOR SUPPORTING MULTIPLE INSTRUCTION SET ARCHITECTURES 有权
标题翻译：多核心处理器支持多种指令集架构
公开(公告)号：US20080059769A1
公开(公告)日：2008-03-06
申请号：US11468547
申请日：2006-08-30
申请人： James Walter Rymarczyk , Michael Ignatowski , Thomas J. Heller
发明人： James Walter Rymarczyk , Michael Ignatowski , Thomas J. Heller
IPC分类号： G06F9/40
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.
摘要翻译：支持多指令集架构的多核处理器为需要多个支持多指令集体系结构（ISAs）的虚拟机环境提供功率高效且灵活的平台。处理器包括具有不同的本地ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。多个核心可以共享公共的第一级高速缓存并且被互斥地选择用于操作，或者可以提供多个一级缓存，一个与每个核心和根据需要运行的核心相关联，包括同时执行不同的ISA。虚拟机管理程序控制核心的操作并定位核心，并且如果需要，当接收到具有指定的ISA的虚拟机的实例化请求时，它可以启用它。

3. 发明申请

US20080147988A1 Multiprocessor System With Dynamic Cache Coherency Regions 审中-公开
标题翻译：具有动态缓存一致性区域的多处理器系统
公开(公告)号：US20080147988A1
公开(公告)日：2008-06-19
申请号：US12037172
申请日：2008-02-26
申请人： Thomas J. Heller , Richard I. Baum , Michael Ignatowski , James W. Rymarczyk
发明人： Thomas J. Heller , Richard I. Baum , Michael Ignatowski , James W. Rymarczyk
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0824
摘要： A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller. The second level controller uses the mode bits to determine which nodes must receive any given transaction that is received by the second level controller. Logical partitions are mapped to allowable physical processors. Cache coherence regions which encompass subsets of the total number of processors and caches in the system are chosen for their physical proximity. A distinct cache coherency region can be defined for each partition using a hypervisor.
摘要翻译：多处理器计算机系统具有多个处理节点，其使用处理器状态信息来确定系统中哪些相干高速缓存需要检查由单个发起处理器的存储请求产生的一致性事务。计算机的节点具有动态一致性边界，使得硬件在任何特定时间点仅使用大型系统中的单个工作负载的总处理器的子集，并且可以在主管软件或固件扩展和收缩时优化高速缓存一致性用于运行任何单个工作负载的处理器数量。节点的多个实例可以与第二级控制器连接，以创建大型多处理器系统。节点控制器使用模式位来确定哪些处理器必须接收节点控制器接收的任何给定事务。第二级控制器使用模式位来确定哪些节点必须接收由第二级控制器接收的任何给定事务。逻辑分区映射到允许的物理处理器。选择包含系统中总处理器和高速缓存的子集的高速缓存相干区域用于物理接近。可以使用管理程序为每个分区定义不同的高速缓存一致性区域。

4. 发明授权

US06595299B2 Method and apparatus for automatically connecting a drive member to a driven member 有权
公开(公告)号：US06595299B2
公开(公告)日：2003-07-22
申请号：US09858624
申请日：2001-05-16
申请人： Thomas J. Heller
发明人： Thomas J. Heller
IPC分类号： A01B59043
CPC分类号： A01B71/063 , A01B59/043 , B60D1/143 , B60D1/62 , B60D2001/008 , B60K17/28
摘要： An apparatus for automatically linking a drive member of a power source and a driven member of an implement, includes two attachment pieces, one attached to the power source, and the other attached to the implement, and an attachment mechanism for automatically connecting the two attachment pieces whereby the drive member and the driven member are operably coupled.

5. 发明授权

US07568060B2 Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses 失效
标题翻译：用于将计算系统的组件与一对单向点对点总线接口的方法和系统
公开(公告)号：US07568060B2
公开(公告)日：2009-07-28
申请号：US11304474
申请日：2005-12-15
申请人： George W. Daly, Jr. , James S. Fields, Jr. , Donald G. Grice , Thomas J. Heller , Appoloniel N. Tankeh
发明人： George W. Daly, Jr. , James S. Fields, Jr. , Donald G. Grice , Thomas J. Heller , Appoloniel N. Tankeh
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/4269
摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.
摘要翻译：提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据，计算系统。该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。该方法还包括：如果从总线控制器可以接收命令包，则在从总线控制器接收到命令分组的第一信令间隔之后，提供用于在从总线控制器向主总线控制器发送确认的装置。

6. 发明授权

US06827154B2 Method and apparatus for automatically connecting a drive member to a driven member 有权
标题翻译：用于将驱动构件自动连接到从动构件的方法和装置
公开(公告)号：US06827154B2
公开(公告)日：2004-12-07
申请号：US10444881
申请日：2003-05-23
申请人： Thomas J. Heller
发明人： Thomas J. Heller
IPC分类号： A01B59043
CPC分类号： A01B71/063 , A01B59/043 , B60D1/143 , B60D1/62 , B60D2001/008 , B60K17/28
摘要： An apparatus for automatically linking a drive member of a power source and a driven member of an implement, includes two attachment pieces, one attached to the power source, and the other attached to the implement, and an attachment mechanism for automatically connecting the two attachment pieces whereby the drive member and the driven member are operably coupled.
摘要翻译：一种用于自动连接电源的驱动构件和工具的从动构件的装置，包括附接到电源的一个附接件和附接到工具的另一个附接件，以及用于自动连接两个附件的附接机构其中驱动构件和从动构件可操作地联接。

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