专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5070450A Power on coordination system and method for multiple processors 失效
标题翻译：多处理器上电协调系统和方法
公开(公告)号：US5070450A
公开(公告)日：1991-12-03
申请号：US532045
申请日：1990-05-25
申请人： Thomas H. Holman, Jr. , David R. Lunsford
发明人： Thomas H. Holman, Jr. , David R. Lunsford
IPC分类号： G06F1/24
CPC分类号： G06F1/24
摘要： A computer system includes a first processor, a second processor, a bus shared by the first processor and the second processor, and a power on reset coordination means for the first processor and the second processor. The power on reset coordination means includes means for resetting the first processor and the second processor, and means for deasserting reset to the first processor and second processor sequentially. It should be noted that in embodiments of the present invention, some "other" processor must be "up" in order to reset the "first" processor or to deassert reset to it.
摘要翻译：计算机系统包括第一处理器，第二处理器，由第一处理器和第二处理器共享的总线，以及用于第一处理器和第二处理器的上电复位协调装置。上电复位协调装置包括用于复位第一处理器和第二处理器的装置，以及用于将第一处理器和第二处理器的复位解除顺序的装置。应当注意，在本发明的实施例中，为了重新设置“第一”处理器或者将其重新置为无效，一些“其他”处理器必须“向上”。

2. 发明授权

US5276832A Computer system having a selectable cache subsystem 失效
标题翻译：具有可选缓存子系统的计算机系统
公开(公告)号：US5276832A
公开(公告)日：1994-01-04
申请号：US541103
申请日：1990-06-19
申请人： Thomas H. Holman, Jr.
发明人： Thomas H. Holman, Jr.
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0864 , G06F2212/601
摘要： A cache subsystem for a computer system which includes a cache memory and a cache control means. When the processor subsystem of the computer system requests data, information related to the location of the data within the memory subsystem of the computer is input to the cache subsystem. The control means receives an address bus bit field and transmits control signals which vary depending on the received address bus bit field to the cache memory to look for the requested data. The address bus bit field is configured based upon the dimensions of the cache memory and includes information as to where the data would be stored within the cache memory. As different cache memories are of different dimensions, means for modifying the address bus bit field generated by the cache control means based on the dimensions of the cache memory are provided so that the cache subsystem may be readily configured to operate with different sized cache memories.
摘要翻译：一种用于计算机系统的缓存子系统，其包括高速缓冲存储器和高速缓存控制装置。当计算机系统的处理器子系统请求数据时，将与计算机的存储器子系统内的数据位置相关的信息输入到缓存子系统。控制装置接收地址总线位字段，并将根据接收的地址总线位字段变化的控制信号发送到高速缓冲存储器以查找所请求的数据。地址总线位字段基于高速缓冲存储器的尺寸配置，并且包括关于数据将被存储在高速缓冲存储器内的位置的信息。由于不同的高速缓冲存储器具有不同的尺寸，因此提供了用于基于高速缓冲存储器的尺寸修改由高速缓存控制装置产生的地址总线位字段的装置，使得高速缓存子系统可以被容易地配置成以不同大小的高速缓冲存储器进行操作。

3. 发明授权

US5261068A Dual path memory retrieval system for an interleaved dynamic RAM memory unit 失效
标题翻译：用于交错动态RAM存储器单元的双路存储器检索系统
公开(公告)号：US5261068A
公开(公告)日：1993-11-09
申请号：US530137
申请日：1990-05-25
申请人： Darius D. Gaskins , Thomas H. Holman, Jr. , Michael L. Longwell , Keith D. Matteson , Terry J. Parks
发明人： Darius D. Gaskins , Thomas H. Holman, Jr. , Michael L. Longwell , Keith D. Matteson , Terry J. Parks
IPC分类号： G06F12/06 , G11C8/12 , G06F12/00 , G11C7/00 , G11C8/00
CPC分类号： G06F12/0607 , G11C8/12
摘要： A digital computer having a dual path memory retrieval system for a dynamic RAM memory unit comprised of any number of interleaved memory banks. The system includes means for asserting and deasserting an access signal to specified locations of the interleaved memory banks, a multiplexer having a pair of input channels for each memory bank and a pair of data paths from the output of each memory bank to the corresponding input channels of the multiplexer. The first data path is a direct path between the memory bank and a first one of the pair of input channels and the second data path is a latched path between the memory bank and a second one of the pair of input channels.
摘要翻译：一种具有用于由任意数量的交错存储器组成的动态RAM存储器单元的双路存储器检索系统的数字计算机。该系统包括用于断言和解除对交错存储体的指定位置的访问信号的装置，具有用于每个存储体的一对输入通道的多路复用器和从每个存储体的输出到相应输入通道的一对数据路径的多路复用器。第一数据路径是存储体与该对输入通道中的第一数据路径之间的直接路径，而第二数据路径是存储体与该对输入通道中的第二个之间的锁存路径。

4. 发明授权

US5506990A Key lock system for personal computer 失效
标题翻译：个人电脑钥匙锁系统
公开(公告)号：US5506990A
公开(公告)日：1996-04-09
申请号：US34041
申请日：1993-03-22
申请人： Thomas H. Holman, Jr.
发明人： Thomas H. Holman, Jr.
IPC分类号： G06F1/24 , G06F1/26
CPC分类号： G06F1/24 , Y10T307/74
摘要： A system for controlling the operation of computer power and reset switches. A separate key switch enables a user to selectively disable the power and reset switches of the computer. The user has the option of operating the computer in a secured mode, in which a user key is required to actuate the power and reset switches, or alternatively in an unsecured mode in which the power and reset switches operate normally. Control circuitry is connected to the switches and operates in the unsecured mode for enabling power supply and reset circuitry operating state transitions responsive to the user actuation of the respective switches. In the secured mode, the circuitry disables the power supply state transitions that normally would occur responsive to user actuation of the first switch, and disables the reset circuitry state transitions, but only from the inactive operating state to the active operating state, so the reset circuitry is prevented from remaining in a continuous reset loop.
摘要翻译：一种用于控制计算机电源和复位开关的操作的系统。单独的钥匙开关使用户能够选择性地禁用电脑的电源和复位开关。用户可以选择在安全模式下操作计算机，其中需要用户密钥来启动电源和复位开关，或者在电源和复位开关正常操作的不安全模式下。控制电路连接到开关并且在不安全模式下操作，以响应于各个开关的用户致动而实现电源和复位电路的操作状态转换。在安全模式下，电路禁用通常会响应于第一开关的用户动作而发生的电源状态转换，并且禁用复位电路状态转换，但是仅从非工作状态转换到主动运行状态，因此复位防止电路保持在连续复位环路中。

5. 发明授权

US5241643A Memory system and associated method for disabling address buffers connected to unused SIMM slots 失效
标题翻译：用于禁用与未使用的SIMM SLOTS连接的地址缓冲区的记忆系统和相关方法
公开(公告)号：US5241643A
公开(公告)日：1993-08-31
申请号：US540651
申请日：1990-06-19
申请人： Michael D. Durkin , Greg N. Stewart , Thomas H. Holman, Jr.
发明人： Michael D. Durkin , Greg N. Stewart , Thomas H. Holman, Jr.
IPC分类号： G06F11/00 , G06F12/06 , G06F12/16 , G11C11/401 , G11C11/408
CPC分类号： G06F12/0684 , Y02B60/1225
摘要： A memory circuit for use in a data processing system is accessed by address signals and includes interconnection circuitry for at least one memory module. The memory circuit further includes an address buffer for transmitting the address signals to the interconnection circuits if and only if the at least one memory module is present. A line interconnects the output enable pin of an address buffer to a grounded PRESENT (PRES) pin on a (single in-line memory module (SIMM) when it is installed in a socket. The line to the address buffer enable pin includes a pull-up resistor portion so that the address buffer is disabled unless a SIMM is connected to the socket.

6. 发明授权

US5555425A Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters 失效
标题翻译：多主机总线仲裁系统，其中公共汽车的地址和数据线可以单独授予各个主机
公开(公告)号：US5555425A
公开(公告)日：1996-09-10
申请号：US490003
申请日：1990-03-07
申请人： Charles P. Zeller , Michael D. Durkin , Thomas H. Holman, Jr.
发明人： Charles P. Zeller , Michael D. Durkin , Thomas H. Holman, Jr.
IPC分类号： G06F9/38 , G06F9/52 , G06F13/36 , G06F13/362 , G06F13/364 , G06F15/16 , G06F15/177
CPC分类号： G06F13/364
摘要： A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter. The requesting master device is transferred into the address master state while the selected master device is still in the data master state, thus performing a pipelining operation.
摘要翻译：多主数字计算机系统具有总线，连接到总线的多个主设备，连接到总线的多个从设备，以及总线控制器，用于仲裁主设备的总线请求，并将总线授予所选择的多个主设备中的一个。每个主设备能够发起总线周期以将数据发送到期望的从设备或从期望的从设备接收数据。总线控制器将总线授予选择的主设备，该主设备进入地址主站状态并寻址所需的从设备。所选择的主设备被传送到总线主机状态，其中发起到或从从设备的数据传输。所选择的主设备然后转移到数据主站状态，除非所选择的主设备想要并且允许通过仲裁器来保持总线的控制。总线控制器通过仲裁器向请求主设备授予总线请求。当选择的主设备仍然处于数据主机状态时，请求主设备被转移到地址主控状态，从而执行流水线操作。

7. 发明授权

US5495584A SCSI bus concatenator/splitter 失效
标题翻译： SCSI总线连接器/分离器
公开(公告)号：US5495584A
公开(公告)日：1996-02-27
申请号：US28506
申请日：1993-03-09
申请人： Thomas H. Holman, Jr. , Peter D. Geiger
发明人： Thomas H. Holman, Jr. , Peter D. Geiger
IPC分类号： G06F13/40 , H03H7/38 , G06F13/00 , H03H11/28 , H04B3/00
CPC分类号： G06F13/409 , H03H7/38
摘要： A system is described for selectively configuring a backplane-based SCSI subsystem in at least two alternative drive configurations. A concatenator/splitter (C/S) device enables a user to concatenate several SCSI devices onto a single bus, or alternatively to split the devices onto multiple buses. In either configuration, the bus or buses are properly terminated. The C/S device is located on the backplane between two buses and is connected to each bus by a connector section. A removable interface module plugs into the connector section in either an upright or upside-down orientation, as selected by the user, to choose either a concatenated or split bus configuration. A terminating network is included in the interface module in order to terminate the first bus when the subsystem is configured in the split bus arrangement.
摘要翻译：描述了一种用于在至少两个备选驱动器配置中选择性地配置基于背板的SCSI子系统的系统。连接器/分离器（C / S）设备使用户能够将多个SCSI设备连接到单个总线上，或者将设备分为多个总线。在任一配置中，总线或总线正确终止。 C / S设备位于两个总线之间的背板上，并通过连接器部分连接到每个总线。可移动接口模块按照用户选择的直立或倒置方向插入连接器部分，以选择级联或分接总线配置。当接口模块中包含一个终端网络，以便在分配总线布置中配置子系统时终止第一个总线。

8. 发明授权

US5452463A Processor and cache controller interface lock jumper 失效
标题翻译：处理器和缓存控制器接口锁定跳线
公开(公告)号：US5452463A
公开(公告)日：1995-09-19
申请号：US119799
申请日：1993-09-10
申请人： Terry J. Parks , Thomas H. Holman, Jr.
发明人： Terry J. Parks , Thomas H. Holman, Jr.
IPC分类号： G06F12/08 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0888
摘要： A computer system including at least one processor and a cache subsystem, in which computer system locked cycles are generated, include a jumper assembly for operatively connecting the at least one processor and the cache subsystem so as to render locked cycles cacheable if the computer system includes only one processor and non-cacheable if the computer system includes more than one processor. A method according to the present invention includes the steps of determining whether there is one or more than one processor in a computer system, and then rendering locked cycles cacheable or non-cacheable accordingly.
摘要翻译：包括生成计算机系统锁定循环的至少一个处理器和高速缓存子系统的计算机系统包括用于可操作地连接至少一个处理器和高速缓存子系统的跳线组件，以便如果计算机系统包括只有一个处理器，如果计算机系统包含多个处理器，则不可缓存。根据本发明的方法包括以下步骤：确定在计算机系统中是否存在一个或多于一个处理器，然后相应地呈现可锁定循环，或者不可高速缓存。

9. 发明授权

US4959777A Write-shared cache circuit for multiprocessor system 失效
标题翻译：多处理器系统的共享缓存电路
公开(公告)号：US4959777A
公开(公告)日：1990-09-25
申请号：US78436
申请日：1987-07-27
申请人： Thomas H. Holman, Jr.
发明人： Thomas H. Holman, Jr.
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0833
摘要： A "write-shared" cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system and by utilizing additional logic in order to enhance the intercache communication. Data is only written through to the system bus when the data is labeled "shared". A write-miss is read only once on the system bus in an "invalidate" cycle, and then it is written only to the requesting cache.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式