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1. 发明授权

US6022596A Method for photoselective seeding and metallization of three-dimensional materials 失效
标题翻译：三维材料的光选播种和金属化方法
公开(公告)号：US6022596A
公开(公告)日：2000-02-08
申请号：US684280
申请日：1996-07-17
申请人： Thomas H. Baum , Luis J. Matienzo , Cindy Reidsema Simpson , Joseph E. Varsik
发明人： Thomas H. Baum , Luis J. Matienzo , Cindy Reidsema Simpson , Joseph E. Varsik
IPC分类号： C23C18/14 , C23C18/26 , H05K3/00 , H05K3/10 , H05K3/18 , H05K3/40 , B05D3/00 , B05D3/04 , B05D3/06 , B05D5/12
CPC分类号： H05K3/105 , C23C18/14 , H05K3/185 , H05K3/403 , H01L2924/0002 , H05K2201/09645 , H05K3/0082 , Y10S428/901 , Y10T428/24917
摘要： A method is provided for selectively metallizing one or more three-dimensional materials in an electronic circuit package comprising the steps of forming a layer of seeding solution on a surface of the three-dimensional material of interest, exposing this layer to light of appropriate wavelength, resulting in the formation of metal seed on regions of the three-dimensional material corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper. Of additional significance, this method is ideal for plating three-dimensional materials such as cone-shaped connectors used in electronic circuit packages.
摘要翻译：提供了一种用于在电子电路封装中选择性地金属化一种或多种三维材料的方法，包括以下步骤：在感兴趣的三维材料的表面上形成接种溶液层，将该层暴露于适当波长的光，导致在与暴露于光的接种溶液层的区域相对应的三维材料的区域上形成金属种子; 通过使接种溶液层的暴露和未曝光区域经受碱溶液来除去接种溶液层的未曝光区域。此后，使用常规技术将另外的金属沉积，例如电镀到金属种子上。重要的是，该方法不涉及光致抗蚀剂或相应的化学显影剂或光致抗蚀剂剥离剂的使用。具有其他意义的是，该方法对于电子电路封装中使用的锥形连接器等三维材料的电镀是理想的。

2. 发明授权

US06210781B1 Method for photoselective seeding and metallization of three-dimensional materials 失效
标题翻译：三维材料的光选播种和金属化方法
公开(公告)号：US06210781B1
公开(公告)日：2001-04-03
申请号：US09459850
申请日：1999-12-13
申请人： Thomas H. Baum , Luis J. Matienzo , Cindy Reidsema Simpson , Joseph E. Varsik
发明人： Thomas H. Baum , Luis J. Matienzo , Cindy Reidsema Simpson , Joseph E. Varsik
IPC分类号： B32B900
CPC分类号： B32B9/00 , C23C18/14 , H01L2924/0002 , H05K3/0082 , H05K3/105 , H05K3/185 , H05K3/403 , H05K2201/09645 , Y10S428/901 , Y10T428/24917 , H01L2924/00
摘要： A method is provided for selectively metallizing one or more three-dimensional materials in an electronic circuit package comprising the steps of forming a layer of seeding solution on a surface of the three-dimensional material of interest, exposing this layer to light of appropriate wavelength, resulting in the formation of metal seed on regions of the three-dimensional material corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper. Of additional significance, this method is ideal for plating three-dimensional materials such as cone-shaped connectors used in electronic circuit packages.
摘要翻译：提供了一种用于在电子电路封装中选择性地金属化一种或多种三维材料的方法，包括以下步骤：在感兴趣的三维材料的表面上形成接种溶液层，将该层暴露于适当波长的光，导致在与暴露于光的接种溶液层的区域相对应的三维材料的区域上形成金属种子; 通过使接种溶液层的暴露和未曝光区域经受碱溶液来除去接种溶液层的未曝光区域。此后，使用常规技术将另外的金属沉积，例如电镀到金属种子上。重要的是，该方法不涉及光致抗蚀剂或相应的化学显影剂或光致抗蚀剂剥离剂的使用。具有其他意义的是，该方法对于电子电路封装中使用的锥形连接器等三维材料的电镀是理想的。

3. 发明授权

US06017613A Method for photoselective seeding and metallization of three-dimensional materials 失效
公开(公告)号：US06017613A
公开(公告)日：2000-01-25
申请号：US736889
申请日：1996-10-25
申请人： Thomas H. Baum , Luis J. Matienzo , Cindy Reidsema Simpson , Joseph E. Varsik
发明人： Thomas H. Baum , Luis J. Matienzo , Cindy Reidsema Simpson , Joseph E. Varsik
IPC分类号： C23C18/14 , C23C18/26 , H05K3/00 , H05K3/10 , H05K3/18 , H05K3/40 , B32B9/00
CPC分类号： H05K3/105 , C23C18/14 , H05K3/185 , H05K3/403 , H01L2924/0002 , H05K2201/09645 , H05K3/0082 , Y10S428/901 , Y10T428/24917
摘要： A method is provided for selectively metallizing one or more three-dimensional materials in an electronic circuit package comprising the steps of forming a layer of seeding solution on a surface of the three-dimensional material of interest, exposing this layer to light of appropriate wavelength, resulting in the formation of metal seed on regions of the three-dimensional material corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper. Of additional significance, this method is ideal for plating three-dimensional materials such as cone-shaped connectors used in electronic circuit packages.

4. 发明授权

US6087258A Method for circuitizing through-holes by photo-activated seeding 失效
标题翻译：通过光激活播种电路化通孔的方法
公开(公告)号：US6087258A
公开(公告)日：2000-07-11
申请号：US764001
申请日：1996-12-12
申请人： Logan Lloyd Simpson , Cindy Reidsema Simpson , Joseph Edward Varsik
发明人： Logan Lloyd Simpson , Cindy Reidsema Simpson , Joseph Edward Varsik
IPC分类号： C23C18/14 , C23C18/26 , H05K3/00 , H05K3/10 , H05K3/18 , H05K3/40 , H01L21/44
CPC分类号： H05K3/105 , C23C18/14 , H05K3/185 , H05K3/403 , H01L2924/0002 , H05K2201/09645 , H05K3/0082 , Y10S428/901 , Y10T428/24917
摘要： A method for selectively metallizing one or more through-holes, other openings (such as slots), or edges of an electronic circuit package comprising the steps of forming a layer of seeding solution on a drilled surface of a substrate of interest exposing this layer to light of appropriate wavelength, through a mask that does not completely cover the through-holes or openings and thereby results in the formation of metal seed on regions of the substrate surface corresponding to the regions of the layer of seeding solution exposed to light; removing the unexposed regions of the layer of seeding solution by subjecting the exposed and unexposed regions of the layer of seeding solution to an alkaline solution. Thereafter, additional metal is deposited, e.g., plated, onto the metal seed using conventional techniques. Significantly, this method does not involve the use of a photoresist, or of a corresponding chemical developer or photoresist stripper. Of additional significance, this method yields plated through-holes or other openings, each of which can accommodate multiple wires, rather then the traditional one wire per through-hole.
摘要翻译：一种用于选择性地金属化一个或多个通孔，电子电路封装的其它开口（例如槽）或边缘的方法，包括以下步骤：在感兴趣的衬底的钻孔表面上形成接种溶液层，从而将该层暴露于通过不完全覆盖通孔或开口的掩模，从而导致在与暴露于光的接种溶液层的区域相对应的基底表面的区域上形成金属种子; 通过使接种溶液层的暴露和未曝光区域经受碱溶液来除去接种溶液层的未曝光区域。此后，使用常规技术将另外的金属沉积，例如电镀到金属种子上。重要的是，该方法不涉及光致抗蚀剂或相应的化学显影剂或光致抗蚀剂剥离剂的使用。具有其他意义的是，该方法产生电镀通孔或其他开口，每个开口可以容纳多条电线，而不是每个通孔的传统单线。

5. 发明授权

US06500324B1 Process for depositing a layer of material on a substrate 有权
标题翻译：在衬底上沉积材料层的工艺
公开(公告)号：US06500324B1
公开(公告)日：2002-12-31
申请号：US09561776
申请日：2000-05-01
申请人： Cindy Reidsema Simpson , Matthew T. Herrick , Gregory S. Etherington , James Derek Legg
发明人： Cindy Reidsema Simpson , Matthew T. Herrick , Gregory S. Etherington , James Derek Legg
IPC分类号： C25D712
CPC分类号： H01L21/2885 , C25D3/665 , C25D5/00 , C25D5/04 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/008 , C25D21/00 , Y10S204/07
摘要： An electroplating system (30) and process makes electrical current density across, a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
摘要翻译：电镀系统（30）和工艺使电流密度跨过半导体器件衬底（20）表面在电镀期间更均匀，以允许更均匀或定制的导电材料沉积。电流密度调节剂（364和37）降低了衬底（20）边缘附近的电流密度。通过降低衬底（20）边缘附近的电流密度，电镀变得更均匀或可以被调整，使得在衬底（20）的中心附近有更多的材料被镀敷。该系统也可以被修改，使得可以去除结构（36）上的电流密度调节部分（364）的材料，而不必拆卸头部（35）的任何部分或以其他方式从系统中移除结构（36）。这种原位清洗可减少设备停机时间，增加设备使用寿命，并减少颗粒数量。

6. 发明授权

US06174425B1 Process for depositing a layer of material over a substrate 失效
标题翻译：在衬底上沉积材料层的工艺
公开(公告)号：US06174425B1
公开(公告)日：2001-01-16
申请号：US08856459
申请日：1997-05-14
申请人： Cindy Reidsema Simpson , Matthew T. Herrick , Gregory S. Etherington , James Derek Legg
发明人： Cindy Reidsema Simpson , Matthew T. Herrick , Gregory S. Etherington , James Derek Legg
IPC分类号： C25D1706
CPC分类号： H01L21/2885 , C25D3/665 , C25D5/00 , C25D5/04 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/008 , C25D21/00 , Y10S204/07
摘要： An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
摘要翻译：电镀系统（30）和工艺使得在电镀期间半导体器件衬底（20）表面上的电流密度更均匀，以允许更均匀或定制的导电材料沉积。电流密度调节剂（364和37）降低了衬底（20）边缘附近的电流密度。通过降低衬底（20）边缘附近的电流密度，电镀变得更均匀或可以被调整，使得在衬底（20）的中心附近有更多的材料被镀敷。该系统也可以被修改，使得可以去除结构（36）上的电流密度调节部分（364）的材料，而不必拆卸头部（35）的任何部分或以其他方式从系统中移除结构（36）。这种原位清洗可减少设备停机时间，增加设备使用寿命，并减少颗粒数量。

7. 发明授权

US07323094B2 Process for depositing a layer of material on a substrate 有权
标题翻译：在衬底上沉积材料层的工艺
公开(公告)号：US07323094B2
公开(公告)日：2008-01-29
申请号：US10218810
申请日：2002-08-14
申请人： Cindy Reidsema Simpson , Matthew T. Herrick , Gregory S. Etherington , James Derek Legg
发明人： Cindy Reidsema Simpson , Matthew T. Herrick , Gregory S. Etherington , James Derek Legg
IPC分类号： C25D5/48 , C25D7/12 , C25D21/00
CPC分类号： H01L21/2885 , C25D3/665 , C25D5/00 , C25D5/04 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/008 , C25D21/00 , Y10S204/07
摘要： An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that plates on electrical current density modifier portions (364) of structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.
摘要翻译：电镀系统（30）和工艺使得在电镀期间半导体器件衬底（20）表面上的电流密度更均匀，以允许更均匀或定制的导电材料沉积。电流密度调节剂（364和37）降低了衬底（20）边缘附近的电流密度。通过降低衬底（20）边缘附近的电流密度，电镀变得更均匀或可以被调整，使得在衬底（20）的中心附近有更多的材料被镀敷。该系统也可以被修改，使得可以去除在结构（36）的电流密度调节部分（364）上的材料，而不必拆卸头部（35）的任何部分或以其他方式从结构（36）移除结构系统。这种原位清洗可减少设备停机时间，增加设备使用寿命，并减少颗粒数量。

8. 发明授权

US06197688B1 Interconnect structure in a semiconductor device and method of formation 失效
公开(公告)号：US06197688B1
公开(公告)日：2001-03-06
申请号：US09022933
申请日：1998-02-12
申请人： Cindy Reidsema Simpson
发明人： Cindy Reidsema Simpson
IPC分类号： H01L2144
CPC分类号： H01L23/53238 , H01L21/2885 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).

9. 发明授权

US06316359B1 Interconnect structure in a semiconductor device and method of formation 有权
标题翻译：半导体器件中的互连结构和形成方法
公开(公告)号：US06316359B1
公开(公告)日：2001-11-13
申请号：US09498613
申请日：2000-02-04
申请人： Cindy Reidsema Simpson
发明人： Cindy Reidsema Simpson
IPC分类号： H01L2144
CPC分类号： H01L23/53238 , H01L21/2885 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).
摘要翻译：在一个实施例中，通过在半导体衬底（10）上沉积介电层（28），在半导体器件中形成导电互连（38）。然后将电介质层（28）图案化以形成互连开口（29）。然后在互连开口（29）内形成氮化钽阻挡层（30）。然后在氮化钽阻挡层（30）上形成包含钯 - 锡胶体的催化剂层（31）。然后将一层无电镀铜（32）沉积在催化层（31）上。然后在化学镀铜层（32）上形成一层电镀铜（34），无电解铜层（32）用作电镀铜层（34）的籽晶层。然后去除电镀铜层（34）的部分以在互连开口（29）内形成铜互连（38）。

10. 发明授权

US06297155B1 Method for forming a copper layer over a semiconductor wafer 有权
标题翻译：在半导体晶片上形成铜层的方法
公开(公告)号：US06297155B1
公开(公告)日：2001-10-02
申请号：US09305093
申请日：1999-05-03
申请人： Cindy Reidsema Simpson , Robert Douglas Mikkola , Matthew T. Herrick , Brett Caroline Baker , David Moralez Pena , Edward Acosta , Rina Chowdhury , Marijean Azrak , Cindy Kay Goldberg , Mohammed Rabiul Islam
发明人： Cindy Reidsema Simpson , Robert Douglas Mikkola , Matthew T. Herrick , Brett Caroline Baker , David Moralez Pena , Edward Acosta , Rina Chowdhury , Marijean Azrak , Cindy Kay Goldberg , Mohammed Rabiul Islam
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/2885
摘要： A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.
摘要翻译：在晶片（20）上电镀铜层（118）的方法以获得改进的铜互连的方式为电镀系统（10）的阴极供电。控制系统（34）以下列两种或多种的混合来为系统（10）的阴极供电：（i）正低功率DC循环（201或254）; （ii）正极大功率直流循环（256或310）; （iii）低功率，脉冲，正功率周期（306或530）; （iv）高功率，脉冲，正动力循环（212,252,302或352）; 和/或（v）负脉冲循环（214,304,510,528或532）。这些循环的收集用于将铜或类似金属（118）电镀到晶片（20）上。在电镀期间，执行基底过程控制和/或终点（506,512或520）以进一步改善所得铜互连。

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