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1. 发明申请

US20130343188A1 EVENT-BASED SHAPER FOR A PACKET SWITCH 有权
标题翻译：用于分组开关的基于事件的形状
公开(公告)号：US20130343188A1
公开(公告)日：2013-12-26
申请号：US13533647
申请日：2012-06-26
申请人： Thomas Frederick Detwiler , Darrin L. Gieger
发明人： Thomas Frederick Detwiler , Darrin L. Gieger
IPC分类号： H04L12/26
CPC分类号： H04L43/16 , H04L47/527 , H04L47/621
摘要： Egress of data packets from a packet switch is controlled in a manner that involves adjusting the shaper accumulators only when a packet egress event or accumulator credit threshold event occurs. A timeline having a number of timeslots is maintained in a memory to mark the times at which events are predicted to occur. If an egress event occurs, in which one or more data packets have been sent from a queue, or if the current timeslot contains a marker, then a count stored in an accumulator is adjusted. If an egress event has occurred or a threshold event in which a count stored in an accumulator has crossed a threshold has occurred, then a marker is stored in a future timeslot.
摘要翻译：来自分组交换机的数据分组的出口以仅在发生分组出口事件或累加器信用阈值事件时才调整整形器累加器的方式进行控制。具有多个时隙的时间线被保存在存储器中以标记事件被预测发生的时间。如果发生了从队列发送一个或多个数据分组的出口事件，或者当前时隙包含标记，则调整存储在累加器中的计数。如果发生了出口事件或存储在累加器中的计数超过阈值的阈值事件，则在未来的时隙中存储标记。

2. 发明授权

US08767542B2 Event-based shaper for a packet switch 有权
标题翻译：用于分组交换机的基于事件的整形器
公开(公告)号：US08767542B2
公开(公告)日：2014-07-01
申请号：US13533647
申请日：2012-06-26
申请人： Thomas Frederick Detwiler , Darrin L. Gieger
发明人： Thomas Frederick Detwiler , Darrin L. Gieger
IPC分类号： H04J1/16 , H04L12/28
CPC分类号： H04L43/16 , H04L47/527 , H04L47/621
摘要： Egress of data packets from a packet switch is controlled in a manner that involves adjusting the shaper accumulators only when a packet egress event or accumulator credit threshold event occurs. A timeline having a number of timeslots is maintained in a memory to mark the times at which events are predicted to occur. If an egress event occurs, in which one or more data packets have been sent from a queue, or if the current timeslot contains a marker, then a count stored in an accumulator is adjusted. If an egress event has occurred or a threshold event in which a count stored in an accumulator has crossed a threshold has occurred, then a marker is stored in a future timeslot.
摘要翻译：来自分组交换机的数据分组的出口以仅在发生分组出口事件或累加器信用阈值事件时才调整整形器累加器的方式进行控制。具有多个时隙的时间线被保存在存储器中以标记事件被预测发生的时间。如果发生了从队列发送一个或多个数据分组的出口事件，或者当前时隙包含标记，则调整存储在累加器中的计数。如果发生了出口事件或存储在累加器中的计数超过阈值的阈值事件，则在未来的时隙中存储标记。

3. 发明授权

US09755746B1 Systems and methods for digitally splitting an optical line terminal across multiple fibers 有权
公开(公告)号：US09755746B1
公开(公告)日：2017-09-05
申请号：US14505677
申请日：2014-10-03
申请人： Thomas Frederick Detwiler
发明人： Thomas Frederick Detwiler
IPC分类号： H04J14/00 , H04B10/00 , H04L12/28 , H04B10/2575 , H04B10/27 , H04B10/40
CPC分类号： H04B10/2575 , H04B10/27 , H04B10/272 , H04B10/40 , H04Q11/0067
摘要： The physical layer of an optical line terminal (OLT) of an optical network is split across multiple fibers so that the OLT has a plurality of optical transceivers for respectively communicating across a plurality of optical fibers. Thus, each optical transceiver is in communication with a smaller number of optical network units (ONUs) relative to an embodiment for which a single optical transceiver is employed, thereby reducing the transmit power requirements of the optical network. Accordingly, less expensive optical components, such as lasers, can be used at the OLT and the ONUs. In addition, the split at the OLT is implemented digitally, and the digital components of the OLT are arranged such that various performance benefits are realized. As an example, the OLT may be configured such that data and/or overhead may be simultaneously transmitted in the upstream direction thereby increasing the upstream throughput and capacity of the optical network.

4. 发明授权

US10044646B1 Systems and methods for efficiently storing packet data in network switches 有权
公开(公告)号：US10044646B1
公开(公告)日：2018-08-07
申请号：US14558674
申请日：2014-12-02
申请人： Thomas Frederick Detwiler
发明人： Thomas Frederick Detwiler
IPC分类号： H04L12/861 , H04L29/06
摘要： A network switch allocates large-scale memory units as data packets are received in order to implement per-queue, circular egress buffers. Each large-scale memory unit is larger than the maximum packet length of the received packets and is capable of storing a plurality of data packets, thereby reducing the number of memory allocation events that are required to process a given number of data packets. Efficient techniques for writing to and reading from the large-scale egress memory units have been developed and may be used to reduce processing delays. Such techniques are compatible with relatively inexpensive memory devices, such as dynamic random access memory (DRAM), that may be separate from the circuitry used to process the data packets. The described architectures are easily scalable so that that a large number of ports (e.g., thousands) may be implemented at a relatively low cost and complexity without introducing significant processing delays.

5. 发明授权

US09942169B1 Systems and methods for efficiently searching for stored data 有权
公开(公告)号：US09942169B1
公开(公告)日：2018-04-10
申请号：US14558679
申请日：2014-12-02
申请人： Thomas Frederick Detwiler
发明人： Thomas Frederick Detwiler
IPC分类号： H04L12/947 , H04L12/741
CPC分类号： H04L49/25 , G06F13/00 , H04L45/745
摘要： A memory system has a plurality of memory stages in which each stage stores a respective portion of a data table. A request for reading an entry of the table is processed serially by the memory stages, and each stage narrows the range of table entries possibly storing the requested data. Based on the results of the previous stages, the final stage is able to quickly determine whether the requested data is stored in the data table and, if so, to retrieve the requested data from such table.

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