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1. 发明授权

US06920525B2 Method and apparatus of local word-line redundancy in CAM 有权
标题翻译： CAM中局部字线冗余的方法和装置
公开(公告)号：US06920525B2
公开(公告)日：2005-07-19
申请号：US10199788
申请日：2002-07-19
申请人： Thomas B. Chadwick , Tarl S. Gordon , Rahul K. Nadkarni , Michael R. Ouellette , Jeremy Rowland
发明人： Thomas B. Chadwick , Tarl S. Gordon , Rahul K. Nadkarni , Michael R. Ouellette , Jeremy Rowland
IPC分类号： G11C15/00 , G11C29/00 , G06F12/00
CPC分类号： G11C29/816 , G11C15/00 , G11C29/848
摘要： A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.
摘要翻译：介绍了实现半导体存储器的字线和匹配线转向的局部字线冗余架构和方法，特别是用于内容寻址存储器（CAM）的本地字线冗余架构和方法。根据本发明，执行本地字线冗余的方法包括：通过使用BIST测试，存储结果，比较失败的读地址数据和失败的匹配行地址数据，以确定冗余是否可能，如果是，则存储冗余修复数据模式和初始化时的装载，从而激活冗余转向。

2. 发明授权

US06552920B2 Saving content addressable memory power through conditional comparisons 有权
标题翻译：通过条件比较保存内容可寻址的内存电源
公开(公告)号：US06552920B2
公开(公告)日：2003-04-22
申请号：US09892396
申请日：2001-06-27
申请人： Thomas B. Chadwick , Tarl S. Gordon , Eric Jasinski , Rahul Nadkarni , Michael R. Ouellette
发明人： Thomas B. Chadwick , Tarl S. Gordon , Eric Jasinski , Rahul Nadkarni , Michael R. Ouellette
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.
摘要翻译：用于改善内容可寻址存储器阵列的方法和结构具有多个串联的存储器子阵列（其包括至少一个存储器单元），连接到每个子阵列的匹配线，有效存储器单元，比较器接收来自匹配线和有效存储器单元的输入，来自比较器的漏线输出和预充电器件。取决于输入数据与存储装置中的数据的比较操作的结果，汇流线和匹配线从第一电压复位到第二电压。当匹配线上出现第二个电压，并且第一个电压出现在漏极线上时，这表示所有子阵列中的数据和输入数据之间的匹配。

3. 发明授权

US06597596B2 Content addressable memory having cascaded sub-entry architecture 有权
公开(公告)号：US06597596B2
公开(公告)日：2003-07-22
申请号：US10286206
申请日：2002-11-01
申请人： Tarl S. Gordon , Rahul K. Nadkarni
发明人： Tarl S. Gordon , Rahul K. Nadkarni
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.

4. 发明授权

US06512684B2 Content addressable memory having cascaded sub-entry architecture 有权
公开(公告)号：US06512684B2
公开(公告)日：2003-01-28
申请号：US09878525
申请日：2001-06-11
申请人： Tarl S. Gordon , Rahul K. Nadkarni
发明人： Tarl S. Gordon , Rahul K. Nadkarni
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.

5. 发明授权

US06618281B1 Content addressable memory (CAM) with error checking and correction (ECC) capability 有权
标题翻译：具有错误检查和校正（ECC）能力的内容可寻址存储器（CAM）
公开(公告)号：US06618281B1
公开(公告)日：2003-09-09
申请号：US10146154
申请日：2002-05-15
申请人： Tarl S. Gordon
发明人： Tarl S. Gordon
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G06F11/1064
摘要： A content addressable memory (CAM) and method capable of ignoring and correcting bit errors contained therein is disclosed. In an exemplary embodiment, the CAM includes a plurality of individual CAM cells for storing a codeword having a number of bits associated therewith. A match line is coupled to each of the plurality of individual CAM cells, and is used to indicate a match status of a comparand word that is compared to the stored codeword. The match status is reflective of either a match state or a mismatch state. A sensing apparatus is used for latching the match line to the match state whenever the comparand word mismatches the stored codeword by a number of N or fewer bits, wherein N is defined a maximum number of correctable bits for a given ECC algorithm used.
摘要翻译：公开了能够忽略和校正其中包含的位错误的内容可寻址存储器（CAM）和方法。在示例性实施例中，CAM包括多个单独的CAM单元，用于存储具有与其相关联的位数的码字。匹配线耦合到多个单独CAM单元中的每一个，并且用于指示与存储的码字进行比较的比较字的匹配状态。匹配状态反映了匹配状态或不匹配状态。只要比较字将存储的码字与存储的码字不匹配多个N个或更少位，则使用感测装置将匹配线锁存到匹配状态，其中N被定义为所使用的给定ECC算法的可校正位的最大数量。

6. 发明申请

US20080159010A1 Multi-use eFuse Macro 审中-公开
标题翻译：多用途eFuse宏
公开(公告)号：US20080159010A1
公开(公告)日：2008-07-03
申请号：US12049307
申请日：2008-03-15
申请人： Tarl S. Gordon , Mack W. Riley
发明人： Tarl S. Gordon , Mack W. Riley
IPC分类号： G11C7/10
CPC分类号： G11C29/56 , G11C17/165 , G11C17/18
摘要： A multi-use eFuse macro is presented. A device includes multiplexers and selection logic that allow eFuse latches to store auxiliary data in addition to programming electronic fuses. The multiplexers and selection logic are coupled to the inputs and outputs of the eFuse latches, and are controlled by a processing unit or an external tester. When a tester wishes to program or update an eFuse element (electronic fuses), the multiplexers and selection logic are configured for “eFuse” mode, which allows an eFuse controller to provide program data and control data to the eFuse latches which, in turn, program the eFuse element. When the device requires additional storage, the multiplexers and selection logic are configured for “auxiliary data” mode, which allows a processing unit to store and retrieve data in the eFuse latches.
摘要翻译：介绍了一种多用途eFuse宏。器件包括多路复用器和选择逻辑，允许eFuse锁存器除了编程电子保险丝之外还存储辅助数据。多路复用器和选择逻辑耦合到eFuse锁存器的输入和输出，并由处理单元或外部测试器控制。当测试者希望编程或更新eFuse元件（电子熔断器）时，多路复用器和选择逻辑被配置为“eFuse”模式，这允许eFuse控制器向eFuse锁存器提供程序数据和控制数据，编程eFuse元素。当设备需要额外的存储时，多路复用器和选择逻辑被配置为“辅助数据”模式，这允许处理单元在eFuse锁存器中存储和检索数据。

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