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1. 发明申请

US20080270962A1 STATIC TIMING SLACKS ANALYSIS AND MODIFICATION 有权
标题翻译：静态时序分析与修改
公开(公告)号：US20080270962A1
公开(公告)日：2008-10-30
申请号：US12138871
申请日：2008-06-13
申请人： Thomas B. Chadwick , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wempie
发明人： Thomas B. Chadwick , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wempie
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

2. 发明授权

US08015526B2 Static timing slacks analysis and modification 有权
标题翻译：静态定时松散分析和修改
公开(公告)号：US08015526B2
公开(公告)日：2011-09-06
申请号：US12138871
申请日：2008-06-13
申请人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
发明人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

3. 发明授权

US07404163B2 Static timing slacks analysis and modification 有权
标题翻译：静态定时松散分析和修改
公开(公告)号：US07404163B2
公开(公告)日：2008-07-22
申请号：US11277385
申请日：2006-03-24
申请人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
发明人： Thomas B. Chadwick, Jr. , Margaret R. Charlebois , David J. Hathaway , Jason E. Rotella , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.
摘要翻译：公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

4. 发明授权

US07142991B2 Voltage dependent parameter analysis 有权
标题翻译：电压相关参数分析
公开(公告)号：US07142991B2
公开(公告)日：2006-11-28
申请号：US11095327
申请日：2005-03-31
申请人： David J. Hathaway , Douglas W. Stout , Ivan L. Wemple
发明人： David J. Hathaway , Douglas W. Stout , Ivan L. Wemple
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a plurality of aggressor objects in the design of the integrated circuit; applying each of the plurality of current waveforms to a subset of the plurality of power bus nodes, the subset of the plurality of power bus nodes being designed to supply power to a corresponding one of the plurality of aggressor objects; determining a plurality of voltage waveforms, each of the plurality of voltage waveforms being at one of the plurality of power bus nodes and corresponding to one of the plurality of current waveforms; using the plurality of voltage waveforms to determine the extreme value.
摘要翻译：提供了一种用于确定集成电路设计的电压相关参数的极值的方法和系统。所述方法包括确定多个电流波形，所述多个波形中的每一个对应于所述集成电路的设计中的多个侵略对象中的一个; 将所述多个电流波形中的每一个应用于所述多个电力总线节点的子集，所述多个电力总线节点的子集被设计为向所述多个侵权者对象中的相应一个提供电力; 确定多个电压波形，所述多个电压波形中的每一个在所述多个电力总线节点中的一个处并且对应于所述多个电流波形中的一个; 使用多个电压波形来确定极值。

5. 发明授权

US09070791B2 Tunable capacitor 有权
标题翻译：可调谐电容
公开(公告)号：US09070791B2
公开(公告)日：2015-06-30
申请号：US11923864
申请日：2007-10-25
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/漏极区域中的电压条件来选择性地在两个不同的值之间改变电容器所呈现的电容值。或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

6. 发明授权

US07821053B2 Tunable capacitor 有权
标题翻译：可调谐电容
公开(公告)号：US07821053B2
公开(公告)日：2010-10-26
申请号：US11560126
申请日：2006-11-15
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/93
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了用作电容器的晶体管的实施例以及在这种电容器内调谐电容的相关联的方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

7. 发明授权

US07619398B2 Programmable on-chip sense line 失效
标题翻译：可编程片上感测线
公开(公告)号：US07619398B2
公开(公告)日：2009-11-17
申请号：US12120255
申请日：2008-05-14
申请人： Corey K. Barrows , Douglas W. Kemerer , Douglas W. Stout , Peter A. Twombly
发明人： Corey K. Barrows , Douglas W. Kemerer , Douglas W. Stout , Peter A. Twombly
IPC分类号： G05F1/40 , H02J13/00 , G05D11/00
CPC分类号： G06F1/26 , Y02P80/14
摘要： Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.
摘要翻译：这里公开了一种用于控制片上配电网络的电源电压的系统。该系统集成了可编程片上感测网络，可在多个位置选择性地连接到配电网络。当感测网络在最佳感测点选择性地连接到配电网络时，产生来自该最佳感测点的局部电压反馈信号并用于调整电源电压，并且因此来管理整个配电网络的电压分布网络。此外，该系统包括用于管理配电网络上的电压分布的策略，用于对配电网络上的压降进行分析的装置以及用于基于策略和配置文件选择最佳感测点的装置。该系统的另一实施例可以进一步控制同一芯片上的多个配电网络的电源电压。

8. 发明授权

US07348657B2 Electrostatic discharge protection networks for triple well semiconductor devices 有权
标题翻译：三阱半导体器件的静电放电保护网络
公开(公告)号：US07348657B2
公开(公告)日：2008-03-25
申请号：US11425491
申请日：2006-06-21
申请人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H01L29/06
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.
摘要翻译：一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。半导体器件优选为二极管结型。

9. 发明授权

US06493257B1 CMOS state saving latch 失效
标题翻译： CMOS状态保存锁存器
公开(公告)号：US06493257B1
公开(公告)日：2002-12-10
申请号：US10108687
申请日：2002-03-27
申请人： Terry C. Coughlin, Jr. , Roger P. Gregor , Steven F. Oakland , Douglas W. Stout
发明人： Terry C. Coughlin, Jr. , Roger P. Gregor , Steven F. Oakland , Douglas W. Stout
IPC分类号： G11C11412
CPC分类号： G11C14/00
摘要： A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.
摘要翻译：一种状态保存电路及其使用方法。电路包括由不间断电源供电的第一锁存器，其中第一锁存器包括用于存储数据的第一对交叉耦合的反相器，并且包括用于隔离第一对交叉耦合的反相器中的数据的输入截止控制; 耦合到所述第一锁存器的输出并由可中断电源供电的第二锁存器，其中所述第二锁存器包括第二对交叉耦合的反相器和用于将所述数据从所述第一锁存器锁存到所述第二锁存器的时钟输入; 并且其中对所述第二锁存器的电力中断导致在所述第一锁存器中保存状态。

10. 发明授权

US6087881A Integrated circuit dual level shift predrive circuit 失效
标题翻译：集成电路双电平偏移预驱动电路
公开(公告)号：US6087881A
公开(公告)日：2000-07-11
申请号：US121515
申请日：1998-07-23
申请人： Francis Chan , Jeffrey H. Sloan , Douglas W. Stout
发明人： Francis Chan , Jeffrey H. Sloan , Douglas W. Stout
IPC分类号： H03K19/003 , H03L5/00
CPC分类号： H03K19/00315
摘要： A dual stage voltage level predrive circuit for an integrated circuit chip including two level shifter stages in series. The voltage level shifting circuit uses single dielectric layer devices and three bias supply circuits each providing a different DC bias voltage for distributing bias voltages among the devices such that dielectric voltage stress across single dielectric layers is reduced. The first stage of the level shifting circuit receives a first input signal having a first voltage swing, converts the first voltage swing to a second voltage swing and provides a first output signal corresponding to the first input signal and having the second voltage swing. The second stage of the level shifting circuit receives the first output signal from the first stage, converts the second voltage swing to a third voltage swing and provides a final output signal having the third voltage swing.
摘要翻译：一种用于集成电路芯片的双级电压电平预调制电路，包括两个电平转换级串联。电压电平移位电路使用单个电介质层器件和三个偏置电源电路，每个偏置电源电路提供不同的直流偏置电压，用于在器件之间分配偏置电压，从而降低跨单个电介质层的介电电压应力。电平移位电路的第一级接收具有第一电压摆幅的第一输入信号，将第一电压摆幅转换为第二电压摆幅，并提供对应于第一输入信号并具有第二电压摆幅的第一输出信号。电平移位电路的第二级接收来自第一级的第一输出信号，将第二电压摆幅转换为第三电压摆幅，并提供具有第三电压摆幅的最终输出信号。

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