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1. 发明申请

US20070284674A1 POROUS SILICON FOR ISOLATION REGION FORMATION AND RELATED STRUCTURE 失效
标题翻译：用于隔离区形成的多孔硅和相关结构
公开(公告)号：US20070284674A1
公开(公告)日：2007-12-13
申请号：US11423286
申请日：2006-06-09
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Kathryn T. Schonenberg , Thomas A. Wallner
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Kathryn T. Schonenberg , Thomas A. Wallner
IPC分类号： H01L29/94
CPC分类号： H01L29/16 , H01L29/66242 , H01L29/7371
摘要： A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base layer extending over a portion of the porous silicon region to form an extrinsic base; and forming an isolation region in the porous silicon region. The method is applicable to forming an HBT having a structure including a crystalline silicon intrinsic base extending beyond a collector region and extending over an isolation region to form a continuous intrinsic-to-extrinsic base conduction path of low resistance. The HBT has improved performance by having a smaller collector to intrinsic base interface and larger intrinsic base to extrinsic base interface.
摘要翻译：公开了使用多孔硅形成隔离区域的方法和相关结构。该方法的一个实施例可以包括形成收集区域; 在集电区域形成多孔硅区域; 在所述集电极区上形成晶体硅本征基极层，所述本征基极层在所述多孔硅区域的一部分上延伸以形成外部基极; 以及在所述多孔硅区域中形成隔离区域。该方法适用于形成具有包括结晶硅本征基底的结构的HBT，该晶体硅本征基极延伸超过集电极区域并在隔离区域上延伸以形成具有低电阻的连续本征至外在的基极传导路径。 HBT通过使内部基本接口具有较小的集电极和较大的内在基极到外部基极接口来提高性能。

2. 发明授权

US07511317B2 Porous silicon for isolation region formation and related structure 失效
标题翻译：多孔硅用于隔离区形成和相关结构
公开(公告)号：US07511317B2
公开(公告)日：2009-03-31
申请号：US11423286
申请日：2006-06-09
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Kathryn T. Schonenberg , Thomas A. Wallner
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Kathryn T. Schonenberg , Thomas A. Wallner
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/16 , H01L29/66242 , H01L29/7371
摘要： A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base layer extending over a portion of the porous silicon region to form an extrinsic base; and forming an isolation region in the porous silicon region. The method is applicable to forming an HBT having a structure including a crystalline silicon intrinsic base extending beyond a collector region and extending over an isolation region to form a continuous intrinsic-to-extrinsic base conduction path of low resistance. The HBT has improved performance by having a smaller collector to intrinsic base interface and larger intrinsic base to extrinsic base interface.
摘要翻译：公开了使用多孔硅形成隔离区域的方法和相关结构。该方法的一个实施例可以包括形成收集区域; 在集电区域形成多孔硅区域; 在所述集电极区上形成晶体硅本征基极层，所述本征基极层在所述多孔硅区域的一部分上延伸以形成外部基极; 以及在所述多孔硅区域中形成隔离区域。该方法适用于形成具有包括结晶硅本征基底的结构的HBT，该晶体硅本征基极延伸超过集电极区域并在隔离区域上延伸以形成具有低电阻的连续本征 - 外在的基极传导路径。 HBT通过使内部基本接口具有较小的集电极和较大的内在基极到外部基极接口来提高性能。

3. 发明授权

US07342293B2 Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same 失效
标题翻译：具有第二浅沟槽隔离（STI）区域的双极结晶体管（BJTS）及其形成方法
公开(公告)号：US07342293B2
公开(公告)日：2008-03-11
申请号：US11164757
申请日：2005-12-05
申请人： Thomas A. Wallner , Thomas N. Adam , Stephen W. Bedell , Joel P. De Souza
发明人： Thomas A. Wallner , Thomas N. Adam , Stephen W. Bedell , Joel P. De Souza
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11 , H01L29/00
CPC分类号： H01L29/732 , H01L29/0649 , H01L29/0657 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/7378
摘要： The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and undercuts a portion of the active base region with an undercut angle of not more than about 90°. For example, the second STI region may a substantially triangular cross-section with an undercut angle of less than about 90°, or a substantially rectangular cross-section with an undercut angle of about 90°. Such a second STI region can be fabricated using a porous surface section formed in an upper surface of the collector region.
摘要翻译：本发明涉及双极结型晶体管（BJTS）。每个BJT的集电极区域位于半导体衬底表面中并且邻近第一浅沟槽隔离（STI）区域。提供了第二STI区域，其在第一STI区域和收集区域之间延伸，并且底切角度不大于约90°的一部分活性基底区域。例如，第二STI区域可以具有小于约90°的底切角的基本上为三角形的横截面，或者具有约90°的底切角的基本上矩形的横截面。可以使用形成在集电区域的上表面中的多孔表面部分来制造这样的第二STI区域。

4. 发明申请

US20110159655A1 STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING 有权
标题翻译：应力增强晶体管器件及其制造方法
公开(公告)号：US20110159655A1
公开(公告)日：2011-06-30
申请号：US13045679
申请日：2011-03-11
申请人： Thomas N. Adam , Judson R. Holt , Thomas A. Wallner
发明人： Thomas N. Adam , Judson R. Holt , Thomas A. Wallner
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26513 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.
摘要翻译：提供了应力增强型晶体管器件及其制造方法。在一个实施例中，晶体管器件包括：栅极导体，设置在一对电介质间隔物之间的半导体衬底之上，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，区域覆盖电介质间隔物以形成通道区域的底切区域; 以及设置在半导体衬底的凹陷区域中的外延源极和漏极区域，并且在电介质间隔物的下方横向延伸到沟道区域的底切区域中。

5. 发明授权

US07521772B2 Monocrystalline extrinsic base and emitter heterojunction bipolar transistor and related methods 有权
标题翻译：单晶外基极和发射极异质结双极晶体管及相关方法
公开(公告)号：US07521772B2
公开(公告)日：2009-04-21
申请号：US11557692
申请日：2006-11-08
申请人： Thomas N Adam , Thomas A. Wallner
发明人： Thomas N Adam , Thomas A. Wallner
IPC分类号： H01L29/00
CPC分类号： H01L29/7378 , H01L29/0821 , H01L29/66242
摘要： A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a heterostructure bipolar transistor (HBT) including: a substrate; a monocrystalline emitter atop the substrate; a collector in the substrate; at least one isolation region adjacent to the collector; a monocrystalline silicon germanium (SiGe) intrinsic base extending over each isolation region; and a monocrystalline silicon extrinsic base. A method may include forming the intrinsic and extrinsic base and the emitter as monocrystalline, with the extrinsic base (and emitter) formed in a self-aligned fashion utilizing selective-epitaxial growth on porous silicon. As a result, some mask levels can be omitted, making this an inexpensive alternative to conventional processing.
摘要翻译：公开了异质结双极晶体管（HBT）及相关方法。在一个实施例中，HBT包括异质结双极晶体管（HBT），包括：衬底; 衬底顶部的单晶发射体; 底物中的收集器; 与收集器相邻的至少一个隔离区域; 在每个隔离区域上延伸的单晶硅锗（SiGe）本征基极; 和单晶硅外在碱。一种方法可以包括将本征和非本征碱和发射体形成为单晶，其中外部碱（和发射体）以自对准方式形成，利用多孔硅上的选择性外延生长。结果，可以省略一些掩模级别，这使得它成为常规处理的便宜的替代方案。

6. 发明申请

US20080121937A1 HETEROJUNCTION BIPOLAR TRANSISTOR WITH MONOCRYSTALLINE BASE AND RELATED METHODS 审中-公开
标题翻译：具有单晶基体的异相双极晶体管及相关方法
公开(公告)号：US20080121937A1
公开(公告)日：2008-05-29
申请号：US11557680
申请日：2006-11-08
申请人： Thomas N Adam , Thomas A. Wallner
发明人： Thomas N Adam , Thomas A. Wallner
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a substrate; a polysilicon emitter atop the substrate; a collector in the substrate; at least one isolation region adjacent to the collector; an intrinsic base including monocrystalline silicon germanium extending over each isolation region; and a monocrystalline extrinsic base. One method includes replacing isolation region formation with formation of porous implanted silicon, which is later converted to a dielectric. As a result, a monocrystalline silicon germanium profile base layer may be formed with extended lateral dimensions over the isolation region(s).
摘要翻译：公开了异质结双极晶体管（HBT）及相关方法。在一个实施例中，HBT包括衬底; 衬底顶部的多晶硅发射体; 底物中的收集器; 与收集器相邻的至少一个隔离区域; 包括在每个隔离区域上延伸的单晶硅锗的本征基底; 和单晶外基。一种方法包括用形成多孔注入的硅代替隔离区形成，后者转化为电介质。结果，可以在隔离区域上形成具有延伸的横向尺寸的单晶硅锗轮廓基底层。

7. 发明申请

US20120326168A1 TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE 审中-公开
标题翻译：带有硅锗锗的晶体管，用于改进的近似控制和优化的形状
公开(公告)号：US20120326168A1
公开(公告)日：2012-12-27
申请号：US13608250
申请日：2012-09-10
申请人： Thomas N. Adam , Judson R. Holt , Alexander Reznicek , Thomas A. Wallner
发明人： Thomas N. Adam , Judson R. Holt , Alexander Reznicek , Thomas A. Wallner
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/66636 , H01L29/66742 , H01L29/7848 , H01L29/78687
摘要： A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.
摘要翻译：一种形成半导体器件的方法，包括在含锗硅层上提供包括半导体层的衬底，并在半导体层的沟道部分的表面上形成栅极结构。阱沟槽被蚀刻到栅极结构的相对侧上的半导体层中。用于形成阱沟槽的蚀刻工艺形成在栅极结构下延伸的底切区域，并且对含锗硅层具有选择性。应力诱导半导体材料被外延生长以填充阱沟槽的至少一部分以提供应力诱导源区域和具有平面基极的应力诱导漏极区域中的至少一个。

8. 发明申请

US20120319166A1 TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE 有权
公开(公告)号：US20120319166A1
公开(公告)日：2012-12-20
申请号：US13161913
申请日：2011-06-16
申请人： Thomas N. Adam , Judson R. Holt , Alexander Reznicek , Thomas A. Wallner
发明人： Thomas N. Adam , Judson R. Holt , Alexander Reznicek , Thomas A. Wallner
IPC分类号： H01L29/78 , H01L29/04 , H01L21/336
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/66636 , H01L29/66742 , H01L29/7848 , H01L29/78687
摘要： A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.

9. 发明授权

US08232172B2 Stress enhanced transistor devices and methods of making 有权
标题翻译：应力增强晶体管器件和制造方法
公开(公告)号：US08232172B2
公开(公告)日：2012-07-31
申请号：US13045679
申请日：2011-03-11
申请人： Thomas N. Adam , Judson R. Holt , Thomas A. Wallner
发明人： Thomas N. Adam , Judson R. Holt , Thomas A. Wallner
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26513 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.
摘要翻译：提供了应力增强型晶体管器件及其制造方法。在一个实施例中，晶体管器件包括：栅极导体，设置在一对电介质间隔物之间的半导体衬底之上，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，区域覆盖电介质间隔物以形成通道区域的底切区域; 以及设置在半导体衬底的凹陷区域中的外延源极和漏极区域，并且在电介质间隔物的下方横向延伸到沟道区域的底切区域中。

10. 发明申请

US20090302348A1 STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING 审中-公开
标题翻译：应力增强晶体管器件及其制造方法
公开(公告)号：US20090302348A1
公开(公告)日：2009-12-10
申请号：US12136195
申请日：2008-06-10
申请人： Thomas N. Adam , Judson R. Holt , Thomas A. Wallner
发明人： Thomas N. Adam , Judson R. Holt , Thomas A. Wallner
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.
摘要翻译：提供了应力增强型晶体管器件及其制造方法。在一个实施例中，晶体管器件包括：栅极导体，设置在一对电介质间隔物之间的半导体衬底之上，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，区域覆盖电介质间隔物以形成通道区域的底切区域; 以及设置在半导体衬底的凹陷区域中的外延源极和漏极区域，并且在电介质间隔物的下方横向延伸到沟道区域的底切区域中。

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