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    • 1. 发明授权
    • Method of forming one or more nanopores for aligning molecules for molecular electronics
    • 形成一个或多个用于分子电子学分子的纳米孔的形成方法
    • US07922927B2
    • 2011-04-12
    • US11906819
    • 2007-10-03
    • Theodore I. KaminsYong ChenPatricia A. Beck
    • Theodore I. KaminsYong ChenPatricia A. Beck
    • C23F1/00
    • B82Y10/00B81C1/00031C03C15/00C03C17/001H01L21/0332H01L21/0337H01L21/31144
    • A technique is provided for forming a molecule or an array of molecules having a defined orientation relative to the substrate or for forming a mold for deposition of a material therein. The array of molecules is formed by dispersing them in an array of small, aligned holes (nanopores), or mold, in a substrate. Typically, the material in which the nanopores are formed is insulating. The underlying substrate may be either conducting or insulating. For electronic device applications, the substrate is, in general, electrically conducting and may be exposed at the bottom of the pores so that one end of the molecule in the nanopore makes electrical contact to the substrate. A substrate such as a single-crystal silicon wafer is especially convenient because many of the process steps to form the molecular array can use techniques well developed for semiconductor device and integrated-circuit fabrication.
    • 提供了一种用于形成具有相对于基底具有限定取向的分子或分子阵列的技术,或用于形成用于在其中沉积材料的模具。 分子阵列通过将它们分散在基底中的小的,对准的孔(纳米孔)或模具的阵列中而形成。 通常,形成纳米孔的材料是绝缘的。 底层衬底可以是导电的或绝缘的。 对于电子器件应用,基底通常是导电的并且可以在孔的底部暴露,使得纳米孔中的分子的一端与基底电接触。 诸如单晶硅晶片的衬底是特别方便的,因为形成分子阵列的许多工艺步骤可以使用用于半导体器件和集成电路制造的技术。
    • 2. 发明申请
    • Method of forming one or more nanopores for aligning molecules for molecular electronics
    • 形成一个或多个用于分子电子学分子的纳米孔的形成方法
    • US20080203055A1
    • 2008-08-28
    • US11906819
    • 2007-10-03
    • Theodore I. KaminsYong ChenPatricia A. Beck
    • Theodore I. KaminsYong ChenPatricia A. Beck
    • B31D3/00
    • B82Y10/00B81C1/00031C03C15/00C03C17/001H01L21/0332H01L21/0337H01L21/31144
    • A technique is provided for forming a molecule or an array of molecules having a defined orientation relative to the substrate or for forming a mold for deposition of a material therein. The array of molecules is formed by dispersing them in an array of small, aligned holes (nanopores), or mold, in a substrate. Typically, the material in which the nanopores are formed is insulating. The underlying substrate may be either conducting or insulating. For electronic device applications, the substrate is, in general, electrically conducting and may be exposed at the bottom of the pores so that one end of the molecule in the nanopore makes electrical contact to the substrate. A substrate such as a single-crystal silicon wafer is especially convenient because many of the process steps to form the molecular array can use techniques well developed for semiconductor device and integrated-circuit fabrication.
    • 提供了一种用于形成具有相对于基底具有限定取向的分子或分子阵列的技术,或用于形成用于在其中沉积材料的模具。 分子阵列通过将它们分散在基底中的小的,对准的孔(纳米孔)或模具的阵列中而形成。 通常,形成纳米孔的材料是绝缘的。 底层衬底可以是导电的或绝缘的。 对于电子器件应用,基底通常是导电的并且可以在孔的底部暴露,使得纳米孔中的分子的一端与基底电接触。 诸如单晶硅晶片的衬底是特别方便的,因为形成分子阵列的许多工艺步骤可以使用用于半导体器件和集成电路制造的技术。
    • 5. 发明授权
    • Formation of nanoscale wires
    • 纳米线的形成
    • US06773616B1
    • 2004-08-10
    • US10033408
    • 2001-12-26
    • Yong ChenDouglas A. A. OhlbergTheodore I. KaminsR. Stanley Williams
    • Yong ChenDouglas A. A. OhlbergTheodore I. KaminsR. Stanley Williams
    • B44C122
    • C30B23/02C30B25/02C30B29/605Y10S977/888
    • Self-organized, or self-assembled, nanowires of a first composition may be used as an etching mask for fabrication of nanowires of a second composition. The method for forming such nanowires comprises: (a) providing an etchable layer of the second composition and having a buried insulating layer beneath a major surface thereof; (b) growing self-assembled nanowires on the surface of the etchable layer; and (c) etching the etchable layer anisotropically down to the insulating layer, using the self-assembled nanowires as a mask. The self-assembled nanowires may be removed or left. In either event, nanowires of the second composition are formed. The method enables the formation of one-dimensional crystalline nanowires with widths and heights at the nanometer scale, and lengths at the micrometer scale, which are aligned along certain crystallographic directions with high crystal quality. Further, the method of the present invention avoids traditional lithography methods, minimizes environmental toxic chemicals usage, simplifies the manufacturing processes, and allows the formation of high-quality one-dimensional nanowires over large areas.
    • 可以将第一组合物的自组织或自组装的纳米线用作用于制造第二组合物的纳米线的蚀刻掩模。 形成这种纳米线的方法包括:(a)提供第二组合物的可蚀刻层,并在其主表面下方具有掩埋绝缘层; (b)在可蚀刻层的表面上生长自组装纳米线; 和(c)使用自组装纳米线作为掩模,各向异性地将可蚀刻层蚀刻到绝缘层。 自组装纳米线可以被去除或留下。 在任一情况下,形成第二组合物的纳米线。 该方法能够形成具有纳米尺度的宽度和高度的一维结晶纳米线,以及在具有高晶体质量的某些晶体方向上对准的微米尺度的长度。 此外,本发明的方法避免了传统的光刻方法,使环境有毒化学品的使用最小化,简化了制造工艺,并且允许在大面积上形成高质量的一维纳米线。
    • 6. 发明授权
    • Method for relieving lattice mismatch stress in semiconductor devices
    • 减少半导体器件晶格失配应力的方法
    • US06211095B1
    • 2001-04-03
    • US09221025
    • 1998-12-23
    • Yong ChenScott W. CorzineTheodore I. KaminsMichael J. LudowisePierre H. MertzShih-Yuan Wang
    • Yong ChenScott W. CorzineTheodore I. KaminsMichael J. LudowisePierre H. MertzShih-Yuan Wang
    • H01L2131
    • H01L21/7624H01L21/02381H01L21/0245H01L21/02488H01L21/02502H01L21/02538H01L21/0254H01L21/02658H01L21/26533
    • A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The first material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the second material by the first material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.
    • 一种用于生长晶体层的方法,其包括在第二材料的晶体衬底的生长表面上的第一材料,其中第一材料和第二材料具有不同的晶格常数。 在衬底中产生掩埋层,使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。 然后在生长温度下将第一种材料沉积在生长表面上。 衬底的隔离层的厚度小于通过第一材料在其上结晶而在第二材料的晶格中引起缺陷的厚度。 掩埋层在生长温度下具有足够的延展性,以允许隔离层的晶格变形,而不使基底的其余部分变形。 本发明可用于在硅衬底上生长III-V半导体材料层。 在硅基基板的情况下,掩埋层优选是在生长温度下足够有韧性的SiO 2,以允许隔离的基底层的变形。
    • 8. 发明授权
    • Integrated circuit substrate that accommodates lattice mismatch stress
    • 集成电路基板,适应晶格失配应力
    • US06429466B2
    • 2002-08-06
    • US09774199
    • 2001-01-29
    • Yong ChenScott W. CorzineTheodore I. KaminsMichael J. LudowisePierre H. MertzShih-Yuan Wang
    • Yong ChenScott W. CorzineTheodore I. KaminsMichael J. LudowisePierre H. MertzShih-Yuan Wang
    • H01L31072
    • H01L21/7624H01L21/02381H01L21/0245H01L21/02488H01L21/02502H01L21/02538H01L21/0254H01L21/02658H01L21/26533
    • A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.
    • 一种用于生长晶体层的方法,其包括在第二材料的晶体衬底的生长表面上的第一材料,其中第一材料和第二材料具有不同的晶格常数。 在衬底中产生掩埋层,使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。 然后将第二种材料在生长温度下沉积在生长表面上。 衬底的隔离层的厚度小于在其上结晶第二材料时在第一材料的晶格中产生缺陷的厚度。 掩埋层在生长温度下具有足够的延展性,以允许隔离层的晶格变形,而不使基底的其余部分变形。 本发明可用于在硅衬底上生长III-V半导体材料层。 在硅基基板的情况下,掩埋层优选是在生长温度下足够有韧性的SiO 2,以允许隔离的基底层的变形。