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1. 发明公开

EP1490969A2 LOW-POWER CMOS FLIP-FLOP 审中-公开
标题翻译： CMOS FLIP具有低功耗FLOPS
公开(公告)号：EP1490969A2
公开(公告)日：2004-12-29
申请号：EP03716979.4
申请日：2003-04-04
申请人： The Regents of The University of Michigan
发明人： ZIESLER, Conrad, H. , PAPAEFTHYMIOU, Marios, C.
IPC分类号： H03K3/037 , H03K3/12 , H03K3/286
CPC分类号： H03K3/356121
摘要： A flip-flop (10) includes a charge storage area (22) that stores a logic voltage indicating a logic state of the flip-flop (10), a first transistor (20a) having a source or drain connected to a clock generating circuit (40), a second transistor (20b) having a source or drain connected to the clock signal generating circuit (40), a clock signal generated by the clock signal generating circuit (40) that is ramped or sinusoidal, and a latching circuit (18) that latches a latch voltage value based on voltages at the first transistor (20a) and the second transistor (20b). The charge storage area (22) supplies a first voltage representing a state of the storage voltage to a gate of the first transistor (20a) and supplies a second voltage to a gate of the second transistor (20b).

2. 发明公开

EP1490876A2 LOW-POWER DRIVER WITH ENERGY RECOVERY 有权
标题翻译：与能量回收的低功耗驱动器
公开(公告)号：EP1490876A2
公开(公告)日：2004-12-29
申请号：EP03726195.5
申请日：2003-04-04
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN
发明人： KIM, Joohee , PAPAEFTHYMIOU, Marios, C.
IPC分类号： G11C8/00
CPC分类号： G11C11/4094 , G11C7/12 , G11C11/4085 , G11C11/417 , G11C11/418 , G11C11/419
摘要： The present invention provides an energy recovering driver (20) that includes a pull-up control (22), a pull-down control (24) and a transmission gate (26). The pull up control (22) is responsive to a pull-up control signal (ch) and a clock signal (PC) to turn the transmission gate (26) ON and OFF and predetermined positions of the clock signal (PC). The pull-down control (24) is responsive to a pull-down control signal (dch) and the clock signal (PC) to turn the transmission gate (26) ON and OFF at other predetermined locations of the clock signal (PC). The transmission gate (26) transmits the clock signal (PC) when at an ON condition and does not transmit the clock signal (PC) when in an OFF condition.

3. 发明授权

EP1490876B1 LOW-POWER DRIVER WITH ENERGY RECOVERY 有权
标题翻译：与能量回收的低功耗驱动器
公开(公告)号：EP1490876B1
公开(公告)日：2010-08-25
申请号：EP03726195.5
申请日：2003-04-04
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN
发明人： KIM, Joohee , PAPAEFTHYMIOU, Marios, C.
IPC分类号： G11C8/00
CPC分类号： G11C11/4094 , G11C7/12 , G11C11/4085 , G11C11/417 , G11C11/418 , G11C11/419

4. 发明申请

WO2003088020A1 CLOCK SIGNAL GENERATING CIRCUIT 审中-公开
标题翻译：时钟信号发生电路
公开(公告)号：WO2003088020A1
公开(公告)日：2003-10-23
申请号：PCT/US2003/010465
申请日：2003-04-04
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN , ZIESLER, Conrad, H. , PAPAEFTHYMIOU, Marios, C.
发明人： ZIESLER, Conrad, H. , PAPAEFTHYMIOU, Marios, C.
IPC分类号： G06F1/04
CPC分类号： G06F1/32 , G06F1/04 , H03K3/356113
摘要： A clock signal generating circuit (40) includes an oscillator portion (302) that sustains a ramped oscillating clock signal in a memory storage device (10) electrically connected to the oscillator portion (302), a switch portion (304) that supplements electrical energy to the oscillator portion (302), and a cycle controller (306) connected to the oscillator portion (302) and the switch portion (304) to supplement energy to the oscillator portion (302) when a peak voltage or current level of the clock signal (PC) falls below a predetermined value.
摘要翻译：时钟信号发生电路（40）包括在电连接到振荡器部分（302）的存储器存储装置（10）中维持斜坡振荡时钟信号的振荡器部分（302），补充电能的开关部分（304）以及连接到振荡器部分（302）和开关部分（304）的周期控制器（306），以在时钟的峰值电压或电流电平时向振荡器部分（302）补充能量信号（PC）下降到预定值以下。

5. 发明申请

WO2003085485A3 LOW-POWER CMOS FLIP-FLOP 审中-公开
公开(公告)号：WO2003085485A3
公开(公告)日：2003-10-16
申请号：PCT/US2003/010320
申请日：2003-04-04
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN , ZIESLER, Conrad, H. , PAPAEFTHYMIOU, Marios, C.
发明人： ZIESLER, Conrad, H. , PAPAEFTHYMIOU, Marios, C.
IPC分类号： H03K3/037
摘要： A flip-flop (10) includes a charge storage area (22) that stores a logic voltage indicating a logic state of the flip-flop (10), a first transistor (20a) having a source or drain connected to a clock generating circuit (40), a second transistor (20b) having a source or drain connected to the clock signal generating circuit (40), a clock signal generated by the clock signal generating circuit (40) that is ramped or sinusoidal, and a latching circuit (18) that latches a latch voltage value based on voltages at the first transistor (20a) and the second transistor (20b). The charge storage area (22) supplies a first voltage representing a state of the storage voltage to a gate of the first transistor (20a) and supplies a second voltage to a gate of the second transistor (20b).

6. 发明申请

WO2003085485A2 LOW-POWER CMOS FLIP-FLOP 审中-公开
标题翻译：低功耗CMOS FLIP-FLOP
公开(公告)号：WO2003085485A2
公开(公告)日：2003-10-16
申请号：PCT/US2003/010320
申请日：2003-04-04
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN , ZIESLER, Conrad, H. , PAPAEFTHYMIOU, Marios, C.
发明人： ZIESLER, Conrad, H. , PAPAEFTHYMIOU, Marios, C.
IPC分类号： G06F
CPC分类号： H03K3/356121
摘要： A flip-flop (10) includes a charge storage area (22) that stores a logic voltage indicating a logic state of the flip-flop (10), a first transistor (20a) having a source or drain connected to a clock generating circuit (40), a second transistor (20b) having a source or drain connected to the clock signal generating circuit (40), a clock signal generated by the clock signal generating circuit (40) that is ramped or sinusoidal, and a latching circuit (18) that latches a latch voltage value based on voltages at the first transistor (20a) and the second transistor (20b). The charge storage area (22) supplies a first voltage representing a state of the storage voltage to a gate of the first transistor (20a) and supplies a second voltage to a gate of the second transistor (20b).
摘要翻译：触发器（10）包括存储指示触发器（10）的逻辑状态的逻辑电压的电荷存储区域（22），具有源极的第一晶体管（20a）或漏极连接到时钟产生电路（40），第二晶体管（20b）具有连接到时钟信号产生电路（40）的源极或漏极，时钟信号产生电路（40）产生的斜坡或正弦曲线，以及基于第一晶体管（20a）和第二晶体管（20b）处的电压锁存锁存电压值的锁存电路（18）。电荷存储区域（22）向第一晶体管（20a）的栅极提供表示存储电压的状态的第一电压并且向第二晶体管（20b）的栅极提供第二电压。

7. 发明申请

WO2006002075A1 ENERGY RECOVERY BOOST LOGIC 审中-公开
标题翻译：能源恢复升压逻辑
公开(公告)号：WO2006002075A1
公开(公告)日：2006-01-05
申请号：PCT/US2005/021073
申请日：2005-06-15
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN , PAPAEFTHYMIOU, Marios, C. , SATHE, Visvesh, Shreeram , ZIESLER, Conrad, Havluj
发明人： PAPAEFTHYMIOU, Marios, C. , SATHE, Visvesh, Shreeram , ZIESLER, Conrad, Havluj
IPC分类号： H03K19/00
CPC分类号： H03K19/0019 , H02M3/158
摘要： A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.
摘要翻译：公开了一种升压电路，其包括连接在时钟信号的互补相位之间的多个晶体管。升压电路还包括连接在所述多个晶体管中的至少两个晶体管之间的第一电节点，其中所述多个晶体管被配置为响应于所述时钟信号从所述电节点处的第一电压产生第二电压。

8. 发明申请

WO2003088459A3 LOW-POWER DRIVER WITH ENERGY RECOVERY 审中-公开
公开(公告)号：WO2003088459A3
公开(公告)日：2003-10-23
申请号：PCT/US2003/010436
申请日：2003-04-04
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN , KIM, Joohee , PAPAEFTHYMIOU, Marios, C.
发明人： KIM, Joohee , PAPAEFTHYMIOU, Marios, C.
IPC分类号： G11C8/00
摘要： The present invention provides an energy recovering driver (20) that includes a pull-up control (22), a pull-down control (24) and a transmission gate (26). The pull up control (22) is responsive to a pull-up control signal (ch) and a clock signal (PC) to turn the transmission gate (26) ON and OFF and predetermined positions of the clock signal (PC). The pull-down control (24) is responsive to a pull-down control signal (dch) and the clock signal (PC) to turn the transmission gate (26) ON and OFF at other predetermined locations of the clock signal (PC). The transmission gate (26) transmits the clock signal (PC) when at an ON condition and does not transmit the clock signal (PC) when in an OFF condition.

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