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1. 发明授权

US08481142B1 System and method for monitoring chloride content and concentration induced by a metal etch process 有权
标题翻译：用于监测由金属蚀刻工艺引起的氯化物含量和浓度的系统和方法
公开(公告)号：US08481142B1
公开(公告)日：2013-07-09
申请号：US11215845
申请日：2005-08-30
申请人： Thanas Budri , Thomas Francis , David Tucker , Stephen W. Swan , Sergei Drizlikh
发明人： Thanas Budri , Thomas Francis , David Tucker , Stephen W. Swan , Sergei Drizlikh
IPC分类号： H01L21/302
CPC分类号： G01N23/223 , G01N2223/076 , H01L21/32136 , H01L22/12 , Y10T428/234
摘要： A system and method for monitoring chloride content and concentration induced by a metal etch process is disclosed. A blank metal film is deposited on a semiconductor wafer. A metal etch process is then applied to partially etch the blank metal film on the wafer. The metal etch process exposes the metal film to chlorine. The wafer is then scanned using surface profiling total X-ray reflection fluorescence. A chlorine concentration map is generated that shows quantitative and spatial information about the chlorine on the wafer. Information from the chlorine concentration map is then used to select a value of chlorine concentration for a metal etch process that will not create metal chloride corrosion on a semiconductor wafer.
摘要翻译：公开了一种用于监测由金属蚀刻工艺引起的氯化物含量和浓度的系统和方法。空白金属膜沉积在半导体晶片上。然后施加金属蚀刻工艺以部分地蚀刻晶片上的空白金属膜。金属蚀刻工艺将金属膜暴露于氯。然后使用表面形貌总X射线反射荧光扫描晶片。产生氯浓度图，其显示关于晶片上的氯的定量和空间信息。然后使用来自氯浓度图的信息来选择不会在半导体晶片上产生金属氯化物腐蚀的金属蚀刻工艺的氯浓度值。

2. 发明授权

US5356828A Method of forming micro-trench isolation regions in the fabrication of semiconductor devices 失效
标题翻译：在半导体器件制造中形成微沟槽隔离区的方法
公开(公告)号：US5356828A
公开(公告)日：1994-10-18
申请号：US86598
申请日：1993-07-01
申请人： Stephen W. Swan , Ellen G. Piccioli
发明人： Stephen W. Swan , Ellen G. Piccioli
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A method of forming micro-trench isolation regions with a separation of 0.20 .mu.m to 0.35 .mu.m in the fabrication of semiconductor devices involves forming an silicon dioxide layer on select locations of a semiconductor substrate and depositing a polysilicon layer onto the silicon dioxide layer. A layer of photoresist is then deposited over select areas of the polysilicon layer and patterned to form micro-trench isolation regions of widths between about 0.2 .mu.m to about 0.5 .mu.m and aspect ratio of between about 2:1 to about 7:1. Thereafter, the isolation regions are etched for a time and pressure sufficient to form micro-trenches in the substrate surface. The micro-trenches will generally have a width ranging from about 1000 .ANG. to about 3500 .ANG. and depth ranging from about 500 .ANG. to about 5000 .ANG.. The layer of photoresist is then removed to expose the polysilicon layer and a channel stop implant is deposited and aligned with the micro-trenches. A thermal silicon dioxide layer is formed in the micro-trenches and an undoped silicon dioxide layer is deposited onto the polysilicon layer to fill the micro-trenches. A planar silicon dioxide layer is then deposited onto the undoped silicon dioxide layer and the undoped and planar silicon dioxide layers are then etched back to expose the polysilicon layer. After etchback, the polysilicon layer is stripped to provide the micro-trench isolation regions.
摘要翻译：在半导体器件的制造中形成分离为0.20μm至0.35μm的微沟槽隔离区域的方法包括在半导体衬底的选择位置上形成二氧化硅层，并在二氧化硅层上沉积多晶硅层。然后将一层光致抗蚀剂沉积在多晶硅层的选择区域上并图案化以形成宽度在约0.2μm至约0.5μm之间的微沟槽隔离区域和约2:1至约7:1的纵横比。此后，隔离区被刻蚀足以在衬底表面形成微沟槽的时间和压力。微沟通常具有从约1000安培到约3500安培的宽度，以及从约500安培到约5000安培的深度。然后去除光致抗蚀剂层以暴露多晶硅层，并且沉积沟槽停止注入并与微沟槽对齐。在微沟槽中形成热二氧化硅层，并且在多晶硅层上沉积未掺杂的二氧化硅层以填充微沟槽。然后将平面二氧化硅层沉积到未掺杂的二氧化硅层上，然后将未掺杂的平面二氧化硅层回蚀以暴露多晶硅层。在回蚀之后，剥离多晶硅层以提供微沟槽隔离区。

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