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1. 发明申请

WO2015103425A1 COMBINING A COARSE ADC AND A SAR ADC 审中-公开
标题翻译：组合一个COARSE ADC和一个SAR ADC
公开(公告)号：WO2015103425A1
公开(公告)日：2015-07-09
申请号：PCT/US2014/073062
申请日：2014-12-31
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： NARAYAN, Subramanian, Jagdish , KANNAN, Anand
IPC分类号： H03M1/38
CPC分类号： H03M1/144 , H03M1/0604 , H03M1/0695 , H03M1/468
摘要： In described examples, a successive approximation register analog to digital converter (SAR ADC) receives an input voltage (102) and multiple reference voltages (105). The SARADC (100) includes a charge sharing DAC (110). The charge sharing DAC (110) includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector (116) is coupled to the charge sharing DAC (110). The zero crossing detector (116) generates a digital output ( 118). A coarse ADC ( 122) receives the input voltage ( 102) and generates a coarse output (124). A predefined offset is added to a residue of the coarse ADC (122). A successive approximation register (SAR) state machine (120) is coupled to the coarse ADC (122) and the zero crossing detector (116) and generates multiple control signals (126). The control signals (126) operate the charge sharing DAC (110) in a sampling mode, an error-correction mode and a conversion mode.
摘要翻译：在所描述的示例中，逐次逼近寄存器模数转换器（SAR ADC）接收输入电压（102）和多个参考电压（105）。 SARADC（100）包括电荷共享DAC（110）。电荷共享DAC（110）包括MSB（最高有效位）电容器阵列和LSB（最低有效位）电容器阵列。零交叉检测器（116）耦合到电荷共享DAC（110）。过零检测器（116）产生数字输出（118）。粗略ADC（122）接收输入电压（102）并产生粗略输出（124）。将预定义的偏移量添加到粗略ADC（122）的残差。逐次逼近寄存器（SAR）状态机（120）耦合到粗略ADC（122）和过零检测器（116）并产生多个控制信号（126）。控制信号（126）以采样模式，纠错模式和转换模式操作电荷共享DAC（110）。

2. 发明申请

WO2020198111A1 ANALOG-TO-DIGITAL CONVERTER WITH DYNAMIC RANGE ENHANCER 审中-公开
公开(公告)号：WO2020198111A1
公开(公告)日：2020-10-01
申请号：PCT/US2020/024156
申请日：2020-03-23
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： AGARWAL, Uttam, Kumar , KANNAN, Anand , VISHWESHWARA, Ramamurthy , SUBRAMANIAN, Anand , GELABERT, Pedro, Ramon , THODI, Diljith, Mathal , PATKI, Abhijit, Anant
IPC分类号： H03M1/12 , H03M3/02
摘要： A circuit (100) includes a programmable gain amplifier (PGA, 102) having a PGA output. The circuit (100) further includes a delta-sigma modulator (104) having an input coupled to the PGA output. The circuit (100) also includes a digital filter (114) and a dynamic range enhancer (DRE) circuit (110). The digital filter (114) is coupled to the delta-sigma modulator output. The DRE circuit (100) is coupled to the delta-sigma modulator output and to the PGA (102). The DRE circuit (110) is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit (110) is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA (102).

3. 发明申请

WO2021026052A1 PROGRAMMABLE GAIN AMPLIFIER WITH PROGRAMMABLE RESISTANCE 审中-公开
公开(公告)号：WO2021026052A1
公开(公告)日：2021-02-11
申请号：PCT/US2020/044702
申请日：2020-08-03
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： SUBRAMANIAN, Anand , HALDER, Tanmay , KANNAN, Anand
IPC分类号： H03F3/00 , H03G1/04
摘要： A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE, 310) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA, 115) having a first PGA input and a second PGA input. The PGA (115) includes a first operational amplifier (OP AMP, OP1) with first and second OP AMP inputs. The AFE (310) also including a programmable resistance circuit (320) having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit (320) includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

4. 发明公开

EP4010979A1 PROGRAMMABLE GAIN AMPLIFIER WITH PROGRAMMABLE RESISTANCE 审中-公开
公开(公告)号：EP4010979A1
公开(公告)日：2022-06-15
申请号：EP20850211.2
申请日：2020-08-03
申请人： Texas Instruments Incorporated
发明人： SUBRAMANIAN, Anand , HALDER, Tanmay , KANNAN, Anand
IPC分类号： H03F3/00 , H03G1/04

5. 发明公开

EP3090488A1 COMBINING A COARSE ADC AND A SAR ADC 有权
标题翻译：组合粗糙和ADC SAR ADC的
公开(公告)号：EP3090488A1
公开(公告)日：2016-11-09
申请号：EP14877496.1
申请日：2014-12-31
申请人： Texas Instruments Incorporated
发明人： NARAYAN, Subramanian, Jagdish , KANNAN, Anand
IPC分类号： H03M1/38
CPC分类号： H03M1/144 , H03M1/0604 , H03M1/0695 , H03M1/468
摘要： In described examples, a successive approximation register analog to digital converter (SAR ADC) receives an input voltage (102) and multiple reference voltages (105). The SARADC (100) includes a charge sharing DAC (110). The charge sharing DAC (110) includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector (116) is coupled to the charge sharing DAC (110). The zero crossing detector (116) generates a digital output ( 118). A coarse ADC ( 122) receives the input voltage ( 102) and generates a coarse output (124). A predefined offset is added to a residue of the coarse ADC (122). A successive approximation register (SAR) state machine (120) is coupled to the coarse ADC (122) and the zero crossing detector (116) and generates multiple control signals (126). The control signals (126) operate the charge sharing DAC (110) in a sampling mode, an error-correction mode and a conversion mode.

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