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1. 发明申请

US20070148874A1 Integrated semiconductor device and method of manufacturing thereof 有权
标题翻译：集成半导体器件及其制造方法
公开(公告)号：US20070148874A1
公开(公告)日：2007-06-28
申请号：US11703628
申请日：2007-02-08
申请人： Tetsuya Nitta , Tomohide Terashima
发明人： Tetsuya Nitta , Tomohide Terashima
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.
摘要翻译：包含具有各自期望的导通电阻和击穿电压的半导体元件的集成半导体器件实现了作为整体的集成半导体元件的适当的特性。集成半导体器件包括形成在半导体层中并且在源极和漏极之间具有n型半导体源，n型半导体的漏极和p型半导体的栅极的多个半导体元件。至少一个半导体元件的漏极的预定部分和另一个半导体元件的漏极的预定部分具有彼此不同的杂质浓度。

2. 发明授权

US07541248B2 Integrated semiconductor device and method of manufacturing thereof 有权
标题翻译：集成半导体器件及其制造方法
公开(公告)号：US07541248B2
公开(公告)日：2009-06-02
申请号：US11703628
申请日：2007-02-08
申请人： Tetsuya Nitta , Tomohide Terashima
发明人： Tetsuya Nitta , Tomohide Terashima
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.
摘要翻译：包含具有各自期望的导通电阻和击穿电压的半导体元件的集成半导体器件实现了作为整体的集成半导体元件的适当的特性。集成半导体器件包括形成在半导体层中并且在源极和漏极之间具有n型半导体源，n型半导体的漏极和p型半导体的栅极的多个半导体元件。至少一个半导体元件的漏极的预定部分和另一个半导体元件的漏极的预定部分具有彼此不同的杂质浓度。

3. 发明授权

US07186623B2 Integrated semiconductor device and method of manufacturing thereof 有权
公开(公告)号：US07186623B2
公开(公告)日：2007-03-06
申请号：US10625733
申请日：2003-07-24
申请人： Tetsuya Nitta , Tomohide Terashima
发明人： Tetsuya Nitta , Tomohide Terashima
IPC分类号： H01L21/331
CPC分类号： H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

4. 发明授权

US07418889B2 Index table assembly 有权
公开(公告)号：US07418889B2
公开(公告)日：2008-09-02
申请号：US10913547
申请日：2004-08-09
申请人： Tetsuya Nitta
发明人： Tetsuya Nitta
IPC分类号： B23Q16/10
CPC分类号： B23Q1/28 , B23Q16/102 , Y10T74/14 , Y10T74/1494
摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.

5. 发明申请

US20080148901A1 Index table assembly 有权
标题翻译：索引表组装
公开(公告)号：US20080148901A1
公开(公告)日：2008-06-26
申请号：US12068933
申请日：2008-02-13
申请人： Tetsuya Nitta
发明人： Tetsuya Nitta
IPC分类号： B23Q16/10
CPC分类号： B23Q1/28 , B23Q16/102 , Y10T74/14 , Y10T74/1494
摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.
摘要翻译：分度台组件包括旋转台，沿旋转台的旋转轴线的方向与旋转台分离的框架，用于通过沿旋转轴线移动旋转台来使旋转台与框架接触的夹紧装置设置在所述转台和所述框架之间的第一轴承以及设置在所述第一轴承与所述旋转台和所述框架中的一个之间的推动装置，并且至少在所述旋转台和所述框架中将所述第一轴承压靠在所述旋转台和所述框架中的另一个上时旋转台旋转。

6. 发明授权

US07339236B2 Semiconductor device, driver circuit and manufacturing method of semiconductor device 有权
标题翻译：半导体器件，驱动电路及半导体器件的制造方法
公开(公告)号：US07339236B2
公开(公告)日：2008-03-04
申请号：US11352344
申请日：2006-02-13
申请人： Tetsuya Nitta , Yasunori Yamashita , Shinichiro Yanagi , Fumitoshi Yamamoto
发明人： Tetsuya Nitta , Yasunori Yamashita , Shinichiro Yanagi , Fumitoshi Yamamoto
IPC分类号： H01L27/01 , H01L29/76 , H01L21/336
CPC分类号： H01L29/78606 , H01L21/84 , H01L27/12 , H01L29/0847 , H01L29/1083 , H01L29/66659 , H01L29/7835 , H01L29/78624
摘要： The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n− type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.
摘要翻译：本发明提供一种半导体技术，能够抑制晶体管的阈值电压的增加，并且还提高源极区域和漏极区域之间的耐受电压。在SOI衬底中的n + O型半导体层中形成p沟道型MOS晶体管的源极和漏极区域。此外，在半导体层中形成n型杂质区。杂质区域形成在源极区域的正下方的源极区域的整个底部上，并且也形成在源极区域和漏极区域之间的半导体层的正下方。将杂质区域中的杂质浓度的峰值位置设定在源极区域和源极区域之间的半导体层的正上方的正下方的源极区域的最下端。

7. 发明申请

US20090200610A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090200610A1
公开(公告)日：2009-08-13
申请号：US12401889
申请日：2009-03-11
申请人： Tetsuya Nitta , Takayuki Igarashi
发明人： Tetsuya Nitta , Takayuki Igarashi
IPC分类号： H01L27/12
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/761 , H01L21/76281 , H01L21/76283 , H01L29/0684 , H01L29/0692 , H01L29/0852 , H01L29/1095 , H01L29/42368 , H01L29/7317 , H01L29/7824 , H01L29/7835 , H01L29/7881 , H01L29/8611
摘要： An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N− layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.
摘要翻译：在半导体衬底上形成有一个BOX层的N层。在N层中，形成沟槽隔离区域以包围N层以成为元件形成区域。沟槽隔离区形成为从N层的表面到达BOX层。在沟槽隔离区域和N层之间形成P型扩散区域10a。连续形成P型扩散区域而不间断地与围绕元件形成区域的沟槽隔离区域的内侧壁的整个表面接触。在N层的元件形成区域中，形成规定的半导体元件。因此，形成了可靠地建立电绝缘的半导体器件，而不增加元件形成区域占据的面积。

8. 发明申请

US20050097976A1 Index table assembly 有权
标题翻译：索引表组装
公开(公告)号：US20050097976A1
公开(公告)日：2005-05-12
申请号：US10889097
申请日：2004-07-13
申请人： Tetsuya Nitta
发明人： Tetsuya Nitta
IPC分类号： B23Q1/00 , B23Q1/26 , B23Q1/52 , B23Q16/02 , F16C19/54 , F16H1/16
CPC分类号： B23Q1/265 , B23Q16/025 , F16C19/545 , F16C2322/39 , Y10T74/14 , Y10T74/19828
摘要： An index table assembly includes a rotary table having a workpiece-receiving surface on one side and a through hole at a rotational center of the rotary table, the through hole having a step portion extending toward the rotational center in the middle of the through hole, a frame separated from the rotary table in the direction of a rotational axis of the rotary table and including a shaft portion extending through the step portion and a bearing support detachably attached to the shaft portion, the bearing support facing a surface of the step portion on the same side as the workpiece-receiving surface, a first bearing positioned between a surface of the rotary table on the side opposite to the workpiece-receiving surface and the frame, and a second bearing positioned between the surface of the step portion on the same side as the workpiece-receiving surface and the bearing support.
摘要翻译：分度台组件包括：旋转台，其具有一侧的工件接收表面和位于旋转台的旋转中心处的通孔，该通孔具有在通孔的中间向着旋转中心延伸的台阶部，在旋转台的旋转轴线方向上与旋转台分离的框架，其包括延伸穿过台阶部分的轴部分和可拆卸地附接到轴部分的轴承支撑件，轴承支撑件面向台阶部分的表面与工件接收表面相同的一侧，位于与工件接收表面相对的一侧上的旋转台的表面与框架之间的第一轴承以及位于该工件接收表面的台阶部分的表面之间的第二轴承侧面作为工件接收面和轴承座。

9. 发明申请

US20150014744A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150014744A1
公开(公告)日：2015-01-15
申请号：US14378720
申请日：2012-02-16
申请人： Mikio Tsujiuchi , Tetsuya Nitta
发明人： Mikio Tsujiuchi , Tetsuya Nitta
IPC分类号： H01L29/739 , H01L29/417
CPC分类号： H01L29/7393 , H01L27/0255 , H01L29/0696 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/41708
摘要： In a current-prioritized IGBT, a collector conductive layer is connected to one collector active region included in a collector region by a plurality of contacts. The number of contacts through which the collector conductive layer is connected to the one collector active region is larger than the number of contacts through which the emitter conductive layer is connected to one base active region included in a base region.
摘要翻译：在电流优先的IGBT中，集电极导电层通过多个触点与包含在集电极区域中的集电极有源区域连接。集电极导电层与一个集电极有源区连接的触点数量大于发射极导体层与包括在基极区域中的一个基极活性区域连接的触点数。

10. 发明授权

US08710619B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08710619B2
公开(公告)日：2014-04-29
申请号：US13208273
申请日：2011-08-11
申请人： Tatsuya Kawamata , Atsushi Tachigami , Kazuya Horie , Tatsuya Shiromoto , Tetsuya Nitta , Hironori Shimizu
发明人： Tatsuya Kawamata , Atsushi Tachigami , Kazuya Horie , Tatsuya Shiromoto , Tetsuya Nitta , Hironori Shimizu
IPC分类号： H01L21/70
CPC分类号： H01L21/76283 , H01L21/3065 , H01L21/76232 , H01L29/7833
摘要： To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 μm. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.
摘要翻译：为了在元件隔离的元件区域的外围设置在SOI衬底上形成的SOI衬底的半导体层的半导体器件中，能够防止因元件隔离引起的可靠性劣化的技术。通过将深沟槽构造沟槽隔离的上部的沟槽宽度设定为小于1.2，可以防止从绝缘膜的上表面填充具有绝缘膜的深沟槽形成的中空部的外观 μm。可以通过在深沟槽的上部形成连接到深沟槽的上部的LOCOS绝缘膜来防止由于深沟槽的上部的沟槽宽度的减小而可能发生的相邻元件区域之间的击穿电压的降低绝缘膜填充在深沟槽中。

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