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2. 发明授权

US5826007A Memory data protection circuit 失效
标题翻译：内存数据保护电路
公开(公告)号：US5826007A
公开(公告)日：1998-10-20
申请号：US785297
申请日：1997-01-21
申请人： Kinya Sakaki , Kimio Mori
发明人： Kinya Sakaki , Kimio Mori
IPC分类号： G01R31/317 , G06F11/267 , G06F12/14 , G06F12/16 , G06F15/78 , G06F21/00 , G06F21/02 , G06F21/24 , G06K19/07 , G06K19/073 , G11C8/20 , G11C29/52 , G06F11/00
CPC分类号： G06F11/2236 , G01R31/31701 , G01R31/31719 , G06F12/1433 , G06F21/79 , G11C8/20 , G11C29/52
摘要： A memory data protection circuit is provided on a one-chip microcomputer having a CPU, ROM, volatile memory, and nonvolatile memory which together with an input/output control circuit are connected to each other via a first bus line. A security flag storage circuit receives a security flag consisting of a plurality of bits. In one state the security flag cannot be rewritten once it has been written. A security flag monitor circuit reads the security flag and when receiving the power-on reset signal recognizes the flag contents. A bus line control circuit controls the connections of the first bus line, a second bus line connected to the ROM, and a third bus line connected to a test-only memory in response to the security flag monitor circuit When the security flag indicates test mode before shipment, the bus line control circuit controls connections so a shift to the test mode may be possible; when it indicates normal operation mode after shipment, a shift to the test mode may be impossible; and when it indicates test mode after shipment, a shift to the test mode may be possible with the ROM disconnected from the second bus line.
摘要翻译：存储器数据保护电路设置在具有CPU，ROM，易失性存储器和非易失性存储器的单片机上，其中输入/输出控制电路经由第一总线彼此连接。安全标志存储电路接收由多个位组成的安全标志。在一个状态下，一旦写入安全标志就不能被重写。安全标志监视电路读取安全标志，并且当接收到上电复位信号时识别标志内容。总线控制电路响应于安全标志监视电路控制第一总线线路，连接到ROM的第二总线线路和连接到仅测试存储器的第三总线的连接。当安全标志指示测试模式时在出货之前，总线控制电路控制连接，从而可能转移到测试模式; 当装运后表示正常运行模式时，转向测试模式可能是不可能的; 并且当它在出货之后指示测试模式时，在ROM与第二总线线路断开的情况下，可以转移到测试模式。

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