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1. 发明授权

US08140836B2 Information processing apparatus and program 有权
标题翻译：信息处理装置和程序
公开(公告)号：US08140836B2
公开(公告)日：2012-03-20
申请号：US12188080
申请日：2008-08-07
申请人： Tomoya Ogawa , Tomohiro Suzuki , Tetsuya Ishikawa , Fumikage Uchida , Munetoshi Eguchi , Hiroaki Yago
发明人： Tomoya Ogawa , Tomohiro Suzuki , Tetsuya Ishikawa , Fumikage Uchida , Munetoshi Eguchi , Hiroaki Yago
IPC分类号： G06F9/24
CPC分类号： G06F11/1417
摘要： If a defect flag stored in a CF 19 while a BIOS is being booted, an information processing device 10 boots a second program stored in an external device 31 connected to a connection section 21, and if the defect flag is not detected, the information processing device 10 confirms whether or not the first program is bootable. If the first program is confirmed to be bootable, the first program is booted and if not, the defect flag is set in the CF 19 and the power of the information processing apparatus 10 is turned off.
摘要翻译：如果在BIOS被引导时存储在CF 19中的缺陷标志，则信息处理设备10启动存储在连接到连接部分21的外部设备31中的第二程序，并且如果未检测到缺陷标志，则信息处理设备10确认第一程序是否可引导。如果第一程序被确认为可引导，则第一程序被引导，如果不是，则在CF 19中设置缺陷标志，并且关闭信息处理设备10的电源。

2. 发明授权

US07953967B2 Information processing apparatus and program 有权
标题翻译：信息处理装置和程序
公开(公告)号：US07953967B2
公开(公告)日：2011-05-31
申请号：US11971599
申请日：2008-01-09
申请人： Tetsuya Ishikawa , Tomohiro Suzuki , Tomoya Ogawa , Fumikage Uchida , Munetoshi Eguchi , Hiroaki Yago
发明人： Tetsuya Ishikawa , Tomohiro Suzuki , Tomoya Ogawa , Fumikage Uchida , Munetoshi Eguchi , Hiroaki Yago
IPC分类号： G06F7/04 , G06F9/00 , G06F9/24 , G06F12/00 , G06F15/177
CPC分类号： G06F21/575
摘要： An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting with a second recording medium from outside; and a controller which determines, during BIOS boot-up operation, whether or not the connection section is connected with the second recording medium which stores predetermined authentication information, and if connected, boots a second program stored in the second recording medium, while if not connected, boots the first program stored in the first recording medium.
摘要翻译：一种信息处理设备，包括：存储第一程序的第一记录介质; 连接部，其能够从外部与第二记录介质连接; 以及控制器，其在BIOS启动操作期间确定所述连接部分是否与存储预定认证信息的所述第二记录介质连接，并且如果连接，则启动存储在所述第二记录介质中的第二程序，如果不是连接，引导存储在第一记录介质中的第一程序。

3. 发明申请

US20080172556A1 INFORMATION PROCESSING APPARATUS AND PROGRAM 有权
标题翻译：信息处理设备和程序
公开(公告)号：US20080172556A1
公开(公告)日：2008-07-17
申请号：US11971599
申请日：2008-01-09
申请人： Tetsuya ISHIKAWA , Tomohiro Suzuki , Tomoya Ogawa , Fumikage Uchida , Munetoshi Eguchi , Hiroaki Yago
发明人： Tetsuya ISHIKAWA , Tomohiro Suzuki , Tomoya Ogawa , Fumikage Uchida , Munetoshi Eguchi , Hiroaki Yago
IPC分类号： G06F15/177 , G06F21/00
CPC分类号： G06F21/575
摘要： An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting with a second recording medium from outside; and a controller which determines, during BIOS boot-up operation, whether or not the connection section is connected with the second recording medium which stores predetermined authentication information, and if connected, boots a second program stored in the second recording medium, while if not connected, boots the first program stored in the first recording medium.
摘要翻译：一种信息处理设备，包括：存储第一程序的第一记录介质; 连接部，其能够从外部与第二记录介质连接; 以及控制器，其在BIOS启动操作期间确定所述连接部分是否与存储预定认证信息的所述第二记录介质连接，并且如果连接，则启动存储在所述第二记录介质中的第二程序，如果不是连接，引导存储在第一记录介质中的第一程序。

4. 发明授权

US08078863B2 Information processing apparatus and program 有权
标题翻译：信息处理装置和程序
公开(公告)号：US08078863B2
公开(公告)日：2011-12-13
申请号：US12188105
申请日：2008-08-07
申请人： Hiroaki Yago , Tomohiro Suzuki , Tetsuya Ishikawa , Tomoya Ogawa , Fumikage Uchida , Munetoshi Eguchi
发明人： Hiroaki Yago , Tomohiro Suzuki , Tetsuya Ishikawa , Tomoya Ogawa , Fumikage Uchida , Munetoshi Eguchi
IPC分类号： G06F7/04 , G06F9/00
CPC分类号： G06F9/4406
摘要： An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting to a second recording medium outside of the information processing apparatus; an instruction input section to input, while the information processing apparatus is in an activated state, an instruction for booting a second program stored in the second recording medium that is connected to the connection section on booting of the BIOS; and a controller which, performs a check when booting of a BIOS, if the second recording medium is connected and the instruction has been input while the information processing apparatus is in an activated state; in case when the second recording medium is connected and the instruction has been input is confirmed, the control section boots the second program; and in case when it is not confirmed, the control section boots the first program.
摘要翻译：一种信息处理设备，包括：存储第一程序的第一记录介质; 连接部，其能够连接到信息处理装置外部的第二记录介质; 指令输入部分，当所述信息处理装置处于激活状态时，输入用于引导存储在所述第二记录介质中的第二程序的指令，所述第二程序在所述BIOS启动时连接到所述连接部分; 以及控制器，当所述信息处理装置处于激活状态时，如果连接了所述第二记录介质并且已经输入了所述指令，则在引导BIOS时执行检查; 在连接第二记录介质并且已经输入指令的情况下，控制部分引导第二程序; 并且在未被确认的情况下，控制部分启动第一程序。

5. 发明申请

US20090150661A1 Information Processing Apparatus and Program 有权
标题翻译：信息处理装置与程序
公开(公告)号：US20090150661A1
公开(公告)日：2009-06-11
申请号：US12188105
申请日：2008-08-07
申请人： Hiroaki Yago , Tomohiro Suzuki , Tatsuya Ishikawa , Tomoya Ogawa , Fumikage Uchida , Munetoshi Eguchi
发明人： Hiroaki Yago , Tomohiro Suzuki , Tatsuya Ishikawa , Tomoya Ogawa , Fumikage Uchida , Munetoshi Eguchi
IPC分类号： G06F9/445
CPC分类号： G06F9/4406
摘要： An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting to a second recording medium outside of the information processing apparatus; an instruction input section to input, while the information processing apparatus is in an activated state, an instruction for booting a second program stored in the second recording medium that is connected to the connection section on booting of the BIOS; and a controller which, performs a check when booting of a BIOS, if the second recording medium is connected and the instruction has been input while the information processing apparatus is in an activated state; in case when the second recording medium is connected and the instruction has been input is confirmed, the control section boots the second program; and in case when it is not confirmed, the control section boots the first program.
摘要翻译：一种信息处理设备，包括：存储第一程序的第一记录介质; 连接部，其能够连接到信息处理装置外部的第二记录介质; 指令输入部分，当所述信息处理装置处于激活状态时，输入用于引导存储在所述第二记录介质中的第二程序的指令，所述第二程序在所述BIOS启动时连接到所述连接部分; 以及控制器，当所述信息处理装置处于激活状态时，如果连接了所述第二记录介质并且已经输入了所述指令，则在引导BIOS时执行检查; 在连接第二记录介质并且已经输入指令的情况下，控制部分引导第二程序; 并且在未被确认的情况下，控制部分启动第一程序。

6. 发明申请

US20080086586A1 INFORMATION PROCESSING APPARATUS AND METHOD FOR SAVING DATA 失效
标题翻译：信息处理装置和数据保存方法
公开(公告)号：US20080086586A1
公开(公告)日：2008-04-10
申请号：US11866641
申请日：2007-10-03
申请人： Tomoya Ogawa , Tomohiro Suzuki , Yuji Tamura , Tetsuya Ishikawa , Hiroyasu Nishimura , Fumikage Uchida , Nao Moromizato , Munetoshi Eguchi , Kenji Okuyama
发明人： Tomoya Ogawa , Tomohiro Suzuki , Yuji Tamura , Tetsuya Ishikawa , Hiroyasu Nishimura , Fumikage Uchida , Nao Moromizato , Munetoshi Eguchi , Kenji Okuyama
IPC分类号： G06F12/16
CPC分类号： G06F11/1441
摘要： An information processing apparatus including: a nonvolatile memory; a volatile system memory in which predetermined data stored in the nonvolatile memory is developed; a control section to save the predetermined data stored in the system memory in the nonvolatile memory when a start of power-off operation is detected; and a storage section that stores a first timing information representing a time point of terminating the operation of saving the predetermined data in the nonvolatile memory, and a second timing information representing a power-off time point, wherein the control section compares the first timing information stored in the storage section with the second timing information, subsequent to the next operation of turning on of the power.
摘要翻译：一种信息处理设备，包括：非易失性存储器; 其中开发存储在非易失性存储器中的预定数据的易失性系统存储器; 控制部分，当检测到电源关闭操作开始时，将存储在系统存储器中的预定数据保存在非易失性存储器中; 以及存储部，其存储表示将所述预定数据保存在所述非易失性存储器中的操作的终止的时刻的第一定时信息和表示断电时间点的第二定时信息，所述控制部将所述第一定时信息存储在具有第二定时信息的存储部分中，在接通电源的下一个操作之后。

7. 发明申请

US20060282466A1 Image processing apparatus and image processing system 有权
公开(公告)号：US20060282466A1
公开(公告)日：2006-12-14
申请号：US11254865
申请日：2005-10-21
申请人： Masayuki Yasukaga , Tomohiro Suzuki , Yuji Tamura , Tetsuya Ishikawa , Hiroyasu Nishimura , Tomoya Ogawa , Fumikage Uchida , Nao Moromizato , Munetoshi Eguchi
发明人： Masayuki Yasukaga , Tomohiro Suzuki , Yuji Tamura , Tetsuya Ishikawa , Hiroyasu Nishimura , Tomoya Ogawa , Fumikage Uchida , Nao Moromizato , Munetoshi Eguchi
IPC分类号： G06F7/00
CPC分类号： H04N1/32101 , G06F21/606 , G06F21/608 , G06F21/6218 , H04N2201/0039 , H04N2201/0094 , H04N2201/3205 , H04N2201/3221 , H04N2201/3226 , H04N2201/3254 , H04N2201/3274 , Y10S707/99945 , Y10S707/99948
摘要： An image processing apparatus comprises an input section which inputs a user identification information; and a registration section which registers an image data in association with the user identification information.

8. 发明申请

US20080162822A1 Memory Apparatus, Cache Control Method, and Cache Control Program 有权
标题翻译：存储器，缓存控制方法和缓存控制程序
公开(公告)号：US20080162822A1
公开(公告)日：2008-07-03
申请号：US11940825
申请日：2007-11-15
申请人： Kenji Okuyama , Tomohiro Suzuki , Yuji Tamura , Tetsuya Ishikawa , Hiroyasu Nishimura , Tomoya Ogawa , Fumikage Uchida , Nao Moromizato , Munetoshi Eguchi
发明人： Kenji Okuyama , Tomohiro Suzuki , Yuji Tamura , Tetsuya Ishikawa , Hiroyasu Nishimura , Tomoya Ogawa , Fumikage Uchida , Nao Moromizato , Munetoshi Eguchi
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F12/0804 , G06F2212/225
摘要： A memory apparatus including: a cache control section to control a cache memory for an auxiliary storage apparatus; a volatile memory; and a nonvolatile memory, wherein the cache memory for the auxiliary storage apparatus is configured to have a volatile cache memory provided in the volatile memory and a nonvolatile cache memory provided in the nonvolatile memory, and wherein the cache control section accesses the nonvolatile cache memory using a write back method.
摘要翻译：一种存储装置，包括：高速缓存控制部分，用于控制辅助存储装置的高速缓冲存储器; 易失记录; 以及非易失性存储器，其中所述辅助存储装置的高速缓冲存储器被配置为具有设置在所述易失性存储器中的易失性高速缓冲存储器和设置在所述非易失性存储器中的非易失性高速缓冲存储器，并且其中所述高速缓存控制部使用回写方法。

9. 发明申请

US20080086659A1 Data processing apparatus and program 有权
标题翻译：数据处理装置和程序
公开(公告)号：US20080086659A1
公开(公告)日：2008-04-10
申请号：US11866718
申请日：2007-10-03
申请人： Tetsuya Ishikawa , Tomohiro Suzuki , Yuji Tamura , Hiroyasu Nishimura , Tomoya Ogawa , Fumikage Uchida , Nao Moromizato , Munetoshi Eguchi , Kenji Okuyama
发明人： Tetsuya Ishikawa , Tomohiro Suzuki , Yuji Tamura , Hiroyasu Nishimura , Tomoya Ogawa , Fumikage Uchida , Nao Moromizato , Munetoshi Eguchi , Kenji Okuyama
IPC分类号： G06F11/00
CPC分类号： G06F11/1441
摘要： A data processing apparatus which saves data in a volatile memory into a nonvolatile memory when power is off, the data processing apparatus including: a detecting circuit for outputting: a momentary interruption detecting signal when a power source voltage is below a first threshold voltage, and a power failure detecting signal when the power source voltage is below a second threshold voltage that is lower than the first threshold voltage; and a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data, and carry out a predetermined shutdown processing when the detecting circuit has output the power failure detecting signal after the detecting circuit has output the momentary interruption detecting signal.
摘要翻译：一种数据处理装置，当电源关闭时，将易失性存储器中的数据保存到非易失性存储器中，所述数据处理装置包括：检测电路，用于在电源电压低于第一阈值电压时输出瞬时中断检测信号;以及当电源电压低于低于第一阈值电压的第二阈值电压时的电源故障检测信号; 以及控制部，其适于在检测电路输出瞬时中断检测信号时开始将易失性存储器中的数据保存到非易失性存储器中，继续保存数据，并且当检测电路具有输出时执行预定的关闭处理检测电路之后的电源故障检测信号输出瞬时中断检测信号。

10. 发明申请

US20070271408A1 Memory administrating method 有权
标题翻译：记忆管理方法
公开(公告)号：US20070271408A1
公开(公告)日：2007-11-22
申请号：US11706247
申请日：2007-02-15
申请人： Hiroyasu Nishimura , Tomohiro Suzuki , Yuji Tamura , Tetsuya Ishikawa , Tomoya Ogawa , Fumikage Uchida , Nao Moromizato , Masayuki Yasukaga , Munetoshi Eguchi
发明人： Hiroyasu Nishimura , Tomohiro Suzuki , Yuji Tamura , Tetsuya Ishikawa , Tomoya Ogawa , Fumikage Uchida , Nao Moromizato , Masayuki Yasukaga , Munetoshi Eguchi
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , Y10S707/99953 , Y10S707/99957
摘要： A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, comprising steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently being in use, determining a usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.
摘要翻译：一种存储器管理方法，用于管理分成多个区域的存储器，每个存储器由连续的存储器地址组成，包括以下步骤：为多个区域的每个区域提供使用信息; 并且当释放当前正在使用的释放目标区域时，基于位于释放目标区域之前和之后的至少一个相邻区域的使用信息来确定释放目标区域的使用。

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