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1. 发明授权

US08451022B2 Integrated circuit and input data controlling method for reconfigurable circuit 有权
标题翻译：用于可重构电路的集成电路和输入数据控制方法
公开(公告)号：US08451022B2
公开(公告)日：2013-05-28
申请号：US11802825
申请日：2007-05-25
申请人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
发明人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.
摘要翻译：根据本发明的集成电路包括可重配置方式包括多个计算单元互连的可重构电路和输入数据控制部分。输入数据控制部分控制输入数据，使得响应于可重构电路的配置将数据输入到可重构电路。

2. 发明申请

US20080079459A1 Integrated circuit and input data controlling method for reconfigurable circuit 有权
标题翻译：用于可重构电路的集成电路和输入数据控制方法
公开(公告)号：US20080079459A1
公开(公告)日：2008-04-03
申请号：US11802825
申请日：2007-05-25
申请人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
发明人： Tetsuo Kawano , Takashi Hanai , Shinichi Sutou
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.
摘要翻译：根据本发明的集成电路包括可重配置方式包括多个计算单元互连的可重构电路和输入数据控制部分。输入数据控制部分控制输入数据，使得响应于可重构电路的配置将数据输入到可重构电路。

3. 发明授权

US09251117B2 Reconfigurable circuit with suspension control circuit 有权
标题翻译：具有悬架控制电路的可重构电路
公开(公告)号：US09251117B2
公开(公告)日：2016-02-02
申请号：US12723320
申请日：2010-03-12
申请人： Takashi Hanai , Shinichi Sutou
发明人： Takashi Hanai , Shinichi Sutou
IPC分类号： G06F9/30 , G06F15/78 , G06F9/38
CPC分类号： G06F15/7867 , G06F9/3897
摘要： A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.
摘要翻译：可重构电路包括可重配算术执行单元阵列，其包括多个算术执行单元和网络电路，以在算术执行单元之间提供可重新配置的连接;悬架控制电路，被配置为控制可重构算术执行单元阵列的操作的暂停和恢复以及缓冲电路，被配置为在暂停所述可重构算术执行单元阵列的操作时临时存储从外部源提供的数据，并且在恢复所述可重构算术执行的操作时将所存储的数据提供给所述可重新配置的算术执行单元阵列单位阵列

4. 发明申请

US20100257335A1 RECONFIGURABLE CIRCUIT WITH SUSPENSION CONTROL CIRCUIT 有权
标题翻译：具有悬挂控制电路的可重新连接电路
公开(公告)号：US20100257335A1
公开(公告)日：2010-10-07
申请号：US12723320
申请日：2010-03-12
申请人： Takashi Hanai , Shinichi Sutou
发明人： Takashi Hanai , Shinichi Sutou
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F15/7867 , G06F9/3897
摘要： A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.
摘要翻译：可重构电路包括可重配算术执行单元阵列，其包括多个算术执行单元和网络电路，以在算术执行单元之间提供可重新配置的连接;悬架控制电路，被配置为控制可重构算术执行单元阵列的操作的暂停和恢复以及缓冲电路，被配置为在暂停所述可重构算术执行单元阵列的操作时临时存储从外部源提供的数据，并且在恢复所述可重构算术执行的操作时将所存储的数据提供给所述可重新配置的算术执行单元阵列单位阵列

5. 发明授权

US09720879B2 Reconfigurable circuit having rows of a matrix of registers connected to corresponding ports and a semiconductor integrated circuit 有权
公开(公告)号：US09720879B2
公开(公告)日：2017-08-01
申请号：US12973730
申请日：2010-12-20
申请人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
发明人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
IPC分类号： G06F15/76 , G06F15/78 , G06F9/30 , G06F9/38
CPC分类号： G06F15/7867 , G06F9/3012 , G06F9/30141 , G06F9/3877
摘要： A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

6. 发明申请

US20090319762A1 DYNAMIC RECONFIGURABLE CIRCUIT AND DATA TRANSMISSION CONTROL METHOD 有权
标题翻译：动态可重构电路和数据传输控制方法
公开(公告)号：US20090319762A1
公开(公告)日：2009-12-24
申请号：US12394863
申请日：2009-02-27
申请人： Takashi HANAI , Shinichi Sutou
发明人： Takashi HANAI , Shinichi Sutou
IPC分类号： G06F9/06
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3879 , G06F9/3891 , G06F9/3897 , G06F15/7867
摘要： A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.
摘要翻译：动态可重构电路包括多个簇，每个簇包括一组可重构处理元件。动态可重构电路能够根据包括处理元件的处理描述和处理元件之间的连接的上下文来动态地改变簇的配置。簇中的第一簇包括信号发生电路，当接收到改变上下文的指令时，产生指示改变上下文的指令的报告信号; 信号添加电路，其将由所述信号发生电路生成的所述报告信号与从所述第一簇发送到第二簇的输出数据相加; 以及数据清除电路，当接收到添加了由第二群集生成的报告信号的输出数据时，执行清除所接收的输出数据的清除处理。

7. 发明申请

US20110246747A1 RECONFIGURABLE CIRCUIT USING VALID SIGNALS AND METHOD OF OPERATING RECONFIGURABLE CIRCUIT 审中-公开
标题翻译：使用有效信号的可重构电路和操作可重新配置电路的方法
公开(公告)号：US20110246747A1
公开(公告)日：2011-10-06
申请号：US13073691
申请日：2011-03-28
申请人： Takashi HANAI , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda , Ichiro Kasama , Kyoji Sato , Shinichi Sutou
发明人： Takashi HANAI , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda , Ichiro Kasama , Kyoji Sato , Shinichi Sutou
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/7867 , G06F9/3897
摘要： A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed.
摘要翻译：可重构电路包括：数据执行单元，包括多个执行元素，每个执行元素在多个数据全部处于有效状态时对多个数据执行执行，并且保存指示执行结果的有效状态输出数据在所有多个数据处于有效状态的输出节点处，被配置为以可重新配置的方式连接执行元件之间的数据选择单元和被配置为向一系列执行元件提供输入数据以执行一系列执行，其中给定数据的有效或无效状态由伴随并与给定数据形成一对的有效信号指定，并且从数据输入单元提供给数据执行单元的输入数据被固定为有效状态执行一系列执行时的常数数据。

8. 发明申请

US20110185152A1 RECONFIGURABLE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：可重构电路和半导体集成电路
公开(公告)号：US20110185152A1
公开(公告)日：2011-07-28
申请号：US12973730
申请日：2010-12-20
申请人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
发明人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
IPC分类号： G06F15/76
CPC分类号： G06F15/7867 , G06F9/3012 , G06F9/30141 , G06F9/3877
摘要： A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.
摘要翻译：可重构电路包括多个处理元件和输入/输出数据接口单元，并且可重构电路被配置为控制每个上下文的多个处理元件的连接。输入/输出数据接口单元被配置为保持输入到多个处理元件的操作输入数据和从多个处理元件输出的操作输出数据。输入/输出数据接口单元包括多个端口和多个寄存器。这些寄存器被配置为连接到多个端口，并且在深度方向上包括m（m为2以上的整数）个组。

9. 发明申请

US20090193239A1 COUNTER CONTROL CIRCUIT, DYNAMIC RECONFIGURABLE CIRCUIT, AND LOOP PROCESSING CONTROL METHOD 审中-公开
标题翻译：计数器控制电路，动态可重构电路和循环处理控制方法
公开(公告)号：US20090193239A1
公开(公告)日：2009-07-30
申请号：US12337694
申请日：2008-12-18
申请人： Takashi HANAI , Shinichi Sutou
发明人： Takashi HANAI , Shinichi Sutou
IPC分类号： G06F9/38
CPC分类号： G06F15/7867 , G06F9/30058 , G06F9/321 , G06F9/3842 , G06F9/3885 , G06F9/3891 , G06F9/3897
摘要： A counter control circuit that controls the operation of a counter arranged in a dynamic reconfigurable circuit executing an arbitrary instruction by dynamically switching an aggregation of reconfigurable processing elements (hereinafter referred to as “PEs”) according to a context reciting a processing content of the PE and a connection content between the PEs, the counter control circuit including: keeping means for keeping an operation instruction signal when the PE executing a conditional branching computation outputs, in a context being adapted to the dynamic reconfigurable circuit, the operation instruction signal of the counter for a subsequent context; output means for outputting the operation instruction signal kept in the keeping means to the counter; and control means for causing the output means to output the operation instruction signal when the context being adapted to the dynamic reconfigurable circuit is switched to the subsequent context.
摘要翻译：一种计数器控制电路，其通过动态地切换可重新配置的处理元件（以下称为“PE”）的集合，控制布置在动态可重构电路中的计数器的操作，所述动态可重构电路根据记录PE的处理内容以及所述PE之间的连接内容，所述计数器控制电路包括：在适于所述动态可重构电路的上下文中，当执行条件分支计算的PE输出时保持操作指令信号的保持装置所述计数器的操作指令信号为后续情况; 输出装置，用于将保存在保持装置中的操作指令信号输出到计数器; 以及控制装置，用于当适配于动态可重构电路的上下文切换到随后的上下文时，使输出装置输出操作指令信号。

10. 发明申请

US20090083527A1 Counter circuit, dynamic reconfigurable circuitry, and loop processing control method 有权
标题翻译：计数器电路，动态可重构电路和循环处理控制方法
公开(公告)号：US20090083527A1
公开(公告)日：2009-03-26
申请号：US12232462
申请日：2008-09-17
申请人： Takashi Hanai , Shinichi Sutou
发明人： Takashi Hanai , Shinichi Sutou
IPC分类号： G06F9/30
CPC分类号： G06F9/325 , G06F9/3842 , G06F9/3885 , G06F9/3897 , G06F15/7867
摘要： A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context, the loop processing content including an output source of an output signal from each of a set of the reconfigured PEs, an output destination of the output signal, and a condition for outputting the output signal to the output destination; and at least one counter circuit including a loop control section and an output register section that implement the set loop processing, that count the number of implementations of the loop processing implemented by the loop control section, and that output the output signal to the output destination based on the counted number of implementations and the condition.
摘要翻译：一种动态可重构电路，其通过根据上下文动态切换可重构处理元件（PE）的处理内容和PE之间的连接内容来实现可选处理，包括：配置寄存器部分，用于在上下文的基础，循环处理内容包括来自一组重新配置的PE中的每一个的输出信号的输出源，输出信号的输出目的地以及用于将输出信号输出到输出目的地的条件; 以及至少一个计数器电路，包括循环控制部分和实现设置循环处理的输出寄存器部分，其对由循环控制部分实现的循环处理的执行次数进行计数，并将输出信号输出到输出目的地基于计数的实施数量和条件。

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