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1. 发明授权

US07694077B2 Multi-port integrated cache 失效
标题翻译：多端口集成缓存
公开(公告)号：US07694077B2
公开(公告)日：2010-04-06
申请号：US12034454
申请日：2008-02-20
申请人： Tetsuo Hironaka , Hans Jürgen Mattausch , Tetsushi Koide , Tai Hirakawa , Koh Johguchi
发明人： Tetsuo Hironaka , Hans Jürgen Mattausch , Tetsushi Koide , Tai Hirakawa , Koh Johguchi
IPC分类号： G06F12/00
CPC分类号： G06F12/0853 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F12/0846 , G06F12/0886
摘要： A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
摘要翻译：提供在并行处理器和主存储器之间并存储有存储在主存储器中的指令和数据的一部分的多端口指令/数据集成高速缓存具有多个存储体，并且多个端口包括指令端口单元由用于访问来自并行处理器的指令的至少一个指令端口和由用于从并行处理器访问数据的至少一个数据端口组成的数据端口单元组成。此外，可以从指令端口指定给存储体的数据宽度被设置为大于可以从数据端口指定给存储体的数据宽度。

2. 发明授权

US07360024B2 Multi-port integrated cache 失效
标题翻译：多端口集成缓存
公开(公告)号：US07360024B2
公开(公告)日：2008-04-15
申请号：US10687460
申请日：2003-10-15
申请人： Tetsuo Hironaka , Hans Jürgen Mattausch , Tetsushi Koide , Tai Hirakawa , Koh Johguchi
发明人： Tetsuo Hironaka , Hans Jürgen Mattausch , Tetsushi Koide , Tai Hirakawa , Koh Johguchi
IPC分类号： G06F12/00
CPC分类号： G06F12/0853 , G06F9/3802 , G06F9/3808 , G06F9/3814 , G06F12/0846 , G06F12/0886
摘要： A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.
摘要翻译：提供在并行处理器和主存储器之间并存储有存储在主存储器中的指令和数据的一部分的多端口指令/数据集成高速缓存具有多个存储体，并且多个端口包括指令端口单元由用于访问来自并行处理器的指令的至少一个指令端口和由用于从并行处理器访问数据的至少一个数据端口组成的数据端口单元组成。此外，可以从指令端口指定给存储体的数据宽度被设置为大于可以从数据端口指定给存储体的数据宽度。

3. 发明授权

US06853251B2 Self-adjusting winner lineup amplifier 失效
标题翻译：自调整优胜者阵容放大器
公开(公告)号：US06853251B2
公开(公告)日：2005-02-08
申请号：US10445033
申请日：2003-05-27
申请人： Hans Jürgen Mattausch , Tetsushi Koide
发明人： Hans Jürgen Mattausch , Tetsushi Koide
IPC分类号： G11C15/04 , G11C15/00 , H03F1/08
CPC分类号： G11C15/00
摘要： A self-adjusting winner lineup amplifier comprising signal control sections which level-control comparison signals (Ci) from word weighted comparators of a memory area, a self-adjusting distance amplifying section corresponding to the respective rows in the memory area which outputs the level-controlled comparison signals (Ci) as distance amplified signals (LAi), a feedback generating section which inputs a self-adjusting voltage (Fa) common to the distance amplifying sections, and a voltage follower which converts its input voltage (min{Ci}; a minimum value of Ci) into a feedback voltage (F) to supply the feedback voltage (F) in parallel and with strong driving current to the signal control sections, wherein amplification characteristics of the distance amplifying section are self-adjusted by a comparison signal (Cwin) of a winner row, and the signal control sections lead the comparison signal (Cwin) into the range of a maximum gain area of the distance amplifying section.
摘要翻译：一种自调整优胜者阵容放大器，包括信号控制部分，该信号控制部分对来自存储区域的字加权比较器的电平控制比较信号（Ci），对应于存储区域中相应行的自调节距离放大部分，控制比较信号（Ci）作为距离放大信号（LAi），反馈产生部分输入距离放大部分共用的自调节电压（Fa）;以及电压跟随器，其转换其输入电压（min {Ci}; 将最小值Ci）转换成反馈电压（F），以向反馈电压（F）并行提供强驱动电流到信号控制部分，其中距离放大部分的放大特性通过比较信号自动调节（Cwin），并且信号控制部分将比较信号（Cwin）引导到距离放大部分的最大增益区域的范围内。

4. 发明申请

US20100179976A1 SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING 审中-公开
标题翻译：执行操作处理的半导体器件
公开(公告)号：US20100179976A1
公开(公告)日：2010-07-15
申请号：US12687756
申请日：2010-01-14
申请人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
发明人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
IPC分类号： G06F7/44 , G06F5/01 , G06F7/552
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
摘要翻译：半导体器件包括：解码器，接收根据布斯（Booth）算法的3比特的第一乘法器数据，指示乘法器输出移位标志，反转标志和操作标志，第一部分乘积计算单元接收2位的第一被乘数数据指示被乘数，移位标志，反转标志和操作标志，以基于移位标志来选择第一被乘数数据的高位位和低位位之一，基于该选择位反转或非反转所选位反转标志，基于操作标志选择反相或非反相数据和预定逻辑电平的数据之一，并将选择的数据作为指示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。

5. 发明授权

US06874068B1 Shared memory 有权
标题翻译：共享内存
公开(公告)号：US06874068B1
公开(公告)日：2005-03-29
申请号：US09500254
申请日：2000-02-08
申请人： Hans Jürgen Mattausch
发明人： Hans Jürgen Mattausch
IPC分类号： G06F15/167 , G06F12/06 , G11C8/16 , G06F12/02 , G06F13/16
CPC分类号： G11C8/16
摘要： A shared memory includes a plurality of multi-port memories each having at least one port with a copybus-function, and at least one port accessible from the user side. At least one copybus is connected to one of the ports with the copybus-function. The shared memory copies contents of one of the multi-port memories, which has been changed by a writing operation from the user side, to other multi-port memories through at least one copybus.
摘要翻译：共享存储器包括多个多端口存储器，每个多端口存储器具有至少一个具有复制总线功能的端口，以及可从用户侧访问的至少一个端口。至少有一个副本总线通过copybus功能连接到其中一个端口。共享存储器通过至少一个副本总线将通过写入操作从用户侧改变的多端口存储器中的一个的内容复制到其他多端口存储器。

6. 发明授权

US06563163B1 Nonvolatile memory using deep level capture of carrier at corner structure of oxide film 失效
标题翻译：非易失性存储器使用氧化膜角结构的载体深层捕获
公开(公告)号：US06563163B1
公开(公告)日：2003-05-13
申请号：US09572239
申请日：2000-05-17
申请人： Michiko Miura , Tsuyoshi Ono , Hans Jürgen Mattausch
发明人： Michiko Miura , Tsuyoshi Ono , Hans Jürgen Mattausch
IPC分类号： H01L2976
CPC分类号： H01L29/792
摘要： In a first surface of a semiconductor substrate, there is formed a step by etching. In the first surface of the substrate, there are also formed source and drain junction regions on respective sides of the step, and source and drain electrodes are formed on the source and drain regions, respectively. An oxide film having a thickness not larger than 10 nm is formed on the first surface of the substrate such that a corner structure corresponding to the step is formed in the oxide film. A gate is formed on the oxide film, a gate electrode is formed on the gate, and a substrate electrode is formed on a second surface of the substrate. Information is stored in the memory by a deep level capture of carriers injected and contained in the oxide film at the corner structure.
摘要翻译：在半导体衬底的第一表面中，通过蚀刻形成一个步骤。在基板的第一表面中，在台阶的两侧还形成有源极和漏极结区域，源极和漏极电极分别形成在源极和漏极区域上。在衬底的第一表面上形成厚度不大于10nm的氧化物膜，使得在氧化物膜中形成与步骤相对应的拐角结构。在氧化膜上形成栅极，在栅极上形成栅电极，在衬底的第二表面上形成衬底电极。通过在拐角结构处注入并包含在氧化物膜中的载流子的深层捕获将信息存储在存储器中。

7. 发明授权

US06516392B1 Address and data transfer circuit 失效
标题翻译：地址和数据传输电路
公开(公告)号：US06516392B1
公开(公告)日：2003-02-04
申请号：US09533336
申请日：2000-03-23
申请人： Hans Jürgen Mattausch
发明人： Hans Jürgen Mattausch
IPC分类号： G06F1200
CPC分类号： G11C8/16
摘要： An address and data transfer circuit includes enable circuit for enabling a single-port memory in accordance with an access requirement from a corresponding port out of a plurality of external ports. An active address selecting circuit selects an address from the corresponding port and transfers the address to the single port memory responsive to activation of the enabling circuit. An active data selecting circuit selects a data from the corresponding port and transfers the data to or from the single port memory, responsive to activation of the enabling circuit.
摘要翻译：地址和数据传输电路包括根据来自多个外部端口中的相应端口的访问要求来启用单端口存储器的使能电路。活动地址选择电路从对应端口选择一个地址，并响应于使能电路的激活将地址传送到单端口存储器。活动数据选择电路从对应端口选择数据，并响应于使能电路的激活将数据传送到单端口存储器或从单端口存储器传送数据。

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