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1. 发明申请

US20060184903A1 Logical equivalence verifying device, logical equivalence verifying method, and logical equivalence verifying program 失效
标题翻译：逻辑等价验证装置，逻辑等效验证方法和逻辑等价验证程序
公开(公告)号：US20060184903A1
公开(公告)日：2006-08-17
申请号：US11398609
申请日：2006-04-06
申请人： Terunobu Maruyama , Hiroji Takeyama , Takeo Nakamura , Mitsuru Satou , Yuki Kumon , Miki Takagi
发明人： Terunobu Maruyama , Hiroji Takeyama , Takeo Nakamura , Mitsuru Satou , Yuki Kumon , Miki Takagi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.
摘要翻译：可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。内部DB 5将结构匹配的结果记录为每个元素的标识符。子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

2. 发明授权

US07337414B2 Logical equivalence verifying device, method, and computer-readable medium thereof 失效
标题翻译：逻辑等价验证装置，方法及其计算机可读介质
公开(公告)号：US07337414B2
公开(公告)日：2008-02-26
申请号：US11398609
申请日：2006-04-06
申请人： Terunobu Maruyama , Hiroji Takeyama , Takeo Nakamura , Mitsuru Satou , Yuki Kumon , Miki Takagi
发明人： Terunobu Maruyama , Hiroji Takeyama , Takeo Nakamura , Mitsuru Satou , Yuki Kumon , Miki Takagi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.
摘要翻译：可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。内部DB 5将结构匹配的结果记录为每个元素的标识符。子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

3. 发明授权

US07143375B2 Logical equivalence verifying device, method and computer readable medium thereof 失效
标题翻译：逻辑等效验证装置，方法和计算机可读介质
公开(公告)号：US07143375B2
公开(公告)日：2006-11-28
申请号：US10705787
申请日：2003-11-12
申请人： Terunobu Maruyama , Hiroji Takeyama , Takeo Nakamura , Mitsuru Satou , Yuki Kumon , Miki Takagi
发明人： Terunobu Maruyama , Hiroji Takeyama , Takeo Nakamura , Mitsuru Satou , Yuki Kumon , Miki Takagi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.
摘要翻译：可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。内部DB 5将结构匹配的结果记录为每个元素的标识符。子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

4. 发明申请

US20060047451A1 Apparatus and method for circuit diagram display, and computer product 审中-公开
标题翻译：电路图显示装置及方法，电脑产品
公开(公告)号：US20060047451A1
公开(公告)日：2006-03-02
申请号：US11022969
申请日：2004-12-28
申请人： Mituru Sato , Yuki Kumon , Hiroji Takeyama , Terunobu Maruyama , Miki Takagi , Tomoki Kanemochi
发明人： Mituru Sato , Yuki Kumon , Hiroji Takeyama , Terunobu Maruyama , Miki Takagi , Tomoki Kanemochi
IPC分类号： G01R13/00
CPC分类号： G06F17/5045
摘要： A circuit diagram display apparatus displays a plurality of logic circuit diagrams. An associating unit associates the logic circuits based on at least any one of identification information, structural information, logical equivalence information, and external designated information about the logic circuits. A display format changing unit changes a display format between a side-by-side format and one-below-the-other format. A display controller performs control to display a target point in the logic circuit diagram in the same position before and after the display format is changed.
摘要翻译：电路图显示装置显示多个逻辑电路图。关联单元基于识别信息，结构信息，逻辑等价信息和关于逻辑电路的外部指定信息中的至少一个来关联逻辑电路。显示格式改变单元改变并排格式和一种在另一种格式之间的显示格式。显示控制器执行控制以在显示格式改变之前和之后在相同位置显示逻辑电路图中的目标点。

5. 发明申请

US20070028203A1 Apparatus and method for creating function verification description, and computer-readable recording medium in which program for creating function verification description is recorded 审中-公开
标题翻译：用于创建功能验证描述的装置和方法，以及其中记录了用于创建功能验证描述的程序的计算机可读记录介质
公开(公告)号：US20070028203A1
公开(公告)日：2007-02-01
申请号：US11258176
申请日：2005-10-26
申请人： Mitsuru Sato , Hiroji Takeyama , Yuki Kumon , Tomoki Kanemochi
发明人： Mitsuru Sato , Hiroji Takeyama , Yuki Kumon , Tomoki Kanemochi
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： To create a function verification description, which is used for verifying a result of simulation performed on a finite state machine, irrespective of description languages of designing an FSM and creating the function verification description even by a person without knowledge of the language and the creation method of the function verification description, there is provided an apparatus including: an extracting section for extracting data concerning a performance that is a subject for the simulation from specification data of the FSM; a retaining section for retaining one or more description templates for function verification descriptions which are associated with one or more performances that are subjects for simulation; a selecting section for selecting a description template corresponding to the first performance; and a creating section for creating the function verifying description by substituting the data concerning the first performance into the particular description template selected.
摘要翻译：为了创建功能验证描述，用于验证在有限状态机上执行的模拟结果，而不管设计FSM的描述语言以及甚至由没有语言知识的人创建功能验证描述和创建方法提供了一种装置，包括：提取部分，用于从FSM的指定数据中提取与模拟对象的性能有关的数据; 一个保留部分，用于保存与作为模拟对象的一个或多个演奏相关联的功能验证描述的一个或多个描述模板; 选择部分，用于选择与第一演奏相对应的描述模板; 以及创建部分，用于通过将关于第一表演的数据替换到所选择的特定描述模板中来创建功能验证描述。

6. 发明授权

US06618834B2 Circuit designing apparatus, circuit designing method and timing distribution apparatus 失效
标题翻译：电路设计装置，电路设计方法和定时分配装置
公开(公告)号：US06618834B2
公开(公告)日：2003-09-09
申请号：US09821487
申请日：2001-03-30
申请人： Hiroji Takeyama , Koichi Itaya , Miki Takagi , Takehiro Yamazaki
发明人： Hiroji Takeyama , Koichi Itaya , Miki Takagi , Takehiro Yamazaki
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , Y10S977/839
摘要： A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.
摘要翻译：电路设计装置包括：电路信息数据库，用于存储有关电路的信息，自动设计处理部，从电路信息数据库中读出与电路信息有关的信息，以及对每个预定处理单元设计电路;设计信息用于存储由自动设计处理部分获得的设计信息，并且包括电路元件的特有信息，表示电路的变化历史和终端负载的历史的变化历史信息以及电路的驱动能力信息。电路设计装置允许自动产生，再生或优化所需的电路。

7. 发明授权

US07086016B2 Method and apparatus for verifying logical equivalency between logic circuits 失效
公开(公告)号：US07086016B2
公开(公告)日：2006-08-01
申请号：US10453662
申请日：2003-06-04
申请人： Kazuhiro Matsuzaki , Hiroji Takeyama , Miki Takagi , Hiroshi Noguchi
发明人： Kazuhiro Matsuzaki , Hiroji Takeyama , Miki Takagi , Hiroshi Noguchi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits includes the steps of converting into a logic circuit a logic cone that has been determined for each of the two logic circuits, the logic cone including all inputs and all logic circuits which affect one output of the combinational logic circuit, storing a logical expression converted by the converting step and a logic circuit element included in the logic cone while correlating the logical expression with the logic circuit element, and specifying the logic circuit element corresponding to a specified term in the logical expression that has been converted.

8. 发明授权

US06678871B2 Circuit designing apparatus, circuit designing method and timing distribution apparatus 失效
标题翻译：电路设计装置，电路设计方法和定时分配装置
公开(公告)号：US06678871B2
公开(公告)日：2004-01-13
申请号：US10237208
申请日：2002-09-09
申请人： Hiroji Takeyama , Koichi Itaya , Miki Takagi , Takehiro Yamazaki
发明人： Hiroji Takeyama , Koichi Itaya , Miki Takagi , Takehiro Yamazaki
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , Y10S977/839
摘要： A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.
摘要翻译：电路设计装置包括：电路信息数据库，用于存储有关电路的信息，自动设计处理部，从电路信息数据库中读出与电路信息有关的信息，以及对每个预定处理单元设计电路;设计信息用于存储由自动设计处理部分获得的设计信息，并且包括电路元件的特有信息，表示电路的变化历史和终端负载的历史的变化历史信息以及电路的驱动能力信息。电路设计装置允许自动产生，再生或优化所需的电路。

9. 发明授权

US06473874B1 Method and system for managing timing error information 失效
标题翻译：用于管理定时错误信息的方法和系统
公开(公告)号：US06473874B1
公开(公告)日：2002-10-29
申请号：US09431461
申请日：1999-11-01
申请人： Hiroji Takeyama
发明人： Hiroji Takeyama
IPC分类号： G06F1100
CPC分类号： G06F17/5031
摘要： The present invention relates to a timing error information managing system. This system comprises a timing error information file, a circuit information file, a correlating section for establishing a correlation between each of timing errors in the timing error information file and each of circuit configurations in the circuit information file, and for adding a circuit information pointer to the timing error information file and further for adding an error information pointer to the circuit information file, and a managing section for managing information on timing errors through the use of the circuit information pointer and the error information pointer. This configuration allows high-efficiency management of the timing error in formation, thereby achieving the speed-up of various kinds of processing using timing error information.
摘要翻译：定时误差信息管理系统技术领域本发明涉及定时误差信息管理系统。该系统包括定时误差信息文件，电路信息文件，用于建立定时误差信息文件中的每个定时误差与电路信息文件中的每个电路配置之间的相关性的相关部分，以及用于将电路信息指针定时错误信息文件，并且还用于向电路信息文件添加错误信息指针，以及管理部分，用于通过使用电路信息指针和错误信息指针来管理关于定时误差的信息。该配置允许高效率地管理定时错误，从而实现使用定时误差信息的各种处理的加速。

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