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1. 发明授权

US4223526A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4223526A
公开(公告)日：1980-09-23
申请号：US874052
申请日：1978-01-31
申请人： Teruaki Tanaka , Masao Kaizuka , Yuichi Takagi , Mitsuo Aihara
发明人： Teruaki Tanaka , Masao Kaizuka , Yuichi Takagi , Mitsuo Aihara
IPC分类号： G04F10/00 , G04G9/00 , G04G9/12 , G04G99/00 , G04B19/30
CPC分类号： G04G9/126 , G04G9/0035
摘要： An electronic timepiece comprises an oscillator, a frequency divider for frequency dividing the output signal of the oscillator to generate 100 Hz output pulse signals, time count circuits having a plurality of counters cascade-connected to count the output pulse signals of the frequency divider, a decoder circuit for decoding the output signal of the time count circuits to generate a display signal and a display device for displaying data corresponding to the output display signal of the decoder circuit, in which a stopwatch display mode and a normal time display mode may be selected by the operation of a switch. The electronic timepiece further includes a control circuit connected between the decoder circuit and display device and adapted to inhibit normal time display data from being supplied to the display device in response to the operation of the switch which sets the electronic timepiece into the stopwatch display mode.
摘要翻译：电子钟表包括振荡器，用于对振荡器的输出信号进行分频以产生100Hz输出脉冲信号的分频器，具有串联连接以对分频器的输出脉冲信号进行计数的多个计数器的时间计数电路，解码器电路，用于解码时间计数电路的输出信号以产生显示信号;以及显示装置，用于显示与解码器电路的输出显示信号相对应的数据，其中可以选择秒表显示模式和正常时间显示模式通过开关的操作。电子表还包括连接在解码器电路和显示装置之间的控制电路，并且适于阻止正常时间显示数据被提供给显示装置，以响应将电子表设置为秒表显示模式的开关的操作。

2. 发明授权

US07233210B2 Spread spectrum clock generator 有权
公开(公告)号：US07233210B2
公开(公告)日：2007-06-19
申请号：US10770643
申请日：2004-02-02
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： H03L7/00
CPC分类号： H04B1/707 , H04B2001/70706
摘要： A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.

3. 发明申请

US20050184774A1 Charge pump 有权
标题翻译：电荷泵
公开(公告)号：US20050184774A1
公开(公告)日：2005-08-25
申请号：US11049421
申请日：2005-02-02
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： H02M5/45 , H03L7/089
CPC分类号： H03L7/0896
摘要： A charge pump that employs a differential amplifier that provides a differential output to control a charge up current source and a charge down current source. The differential amplifier is configured so that the current sources can maintain substantially equal charge up current and charge down current irrespective of the voltage at its output terminal.
摘要翻译：电荷泵采用差分放大器，提供差分输出来控制充电电流源和充电电流源。差分放大器被配置为使得电流源可以保持基本相等的充电电流和充电停止电流，而与其输出端子处的电压无关。

4. 发明授权

US07609104B2 Spread spectrum clock generator 有权
标题翻译：扩频时钟发生器
公开(公告)号：US07609104B2
公开(公告)日：2009-10-27
申请号：US11553300
申请日：2006-10-26
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A digitally controlled delay line generates a clock signal. The clock signal can be modulates as a spread spectrum clock signal. In an example embodiment, the programmable delay line has an input for receiving a signal, an output that delays outputting the input signal by a time period programmed into a delay value input. A feedback loop comprising an inverter is coupled between the input and the output of the programmable delay line.
摘要翻译：数字控制延时线产生时钟信号。时钟信号可以作为扩频时钟信号进行调制。在示例性实施例中，可编程延迟线具有用于接收信号的输入端，输出端延迟输出信号经过编程到延迟值输入端的时间段。包括反相器的反馈回路耦合在可编程延迟线的输入和输出之间。

5. 发明申请

US20050069019A1 Spread spectrum clock generator 有权
标题翻译：扩频时钟发生器
公开(公告)号：US20050069019A1
公开(公告)日：2005-03-31
申请号：US10647929
申请日：2003-08-26
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： H04B1/707 , H04B1/69
CPC分类号： H04B1/707 , H04B2001/70706
摘要： A clock signal generator varies a frequency of a digital clock over a selected range of frequencies. The generator employs a divider for lowering a frequency of a clock signal. A counter increments synchronously with the signal, and causes a selected sequence of outputs to be generated by a pattern generator. The pattern generator output forms an input to a digitally controllable delay line which receives the lower frequency clock signal. The pattern generator causes the digital delay line to vary a frequency of the lowered frequency clock signal between selected boundaries. The varying frequency clock signal is then raised up again such that a final clock has a varying frequency, and will exhibit less EMI spiking during switching of an associated, synchronous digital data device. The solid state nature of the generator allows for simple fabrication, inexpensive manufacture and ready integration into digital circuitry, such as multifunction integrated circuits.
摘要翻译：时钟信号发生器在选定的频率范围内改变数字时钟的频率。发生器采用分频器来降低时钟信号的频率。计数器与该信号同步地增加，并且使得所选择的输出序列由模式发生器产生。模式发生器输出形成输入到数字可控延迟线，其接收较低频率时钟信号。模式发生器使数字延迟线改变选定边界之间降低的频率时钟信号的频率。然后，变化的频率时钟信号再次升高，使得最终时钟具有变化的频率，并且在相关联的同步数字数据设备的切换期间将表现出较少的EMI尖峰。发电机的固态性质允许简单的制造，廉价的制造和就绪的集成到诸如多功能集成电路的数字电路中。

6. 发明授权

US07702056B2 Time base corrector 有权
标题翻译：时基校正器
公开(公告)号：US07702056B2
公开(公告)日：2010-04-20
申请号：US11553320
申请日：2006-10-26
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： H04L7/00 , H04N7/12 , H03L7/00
CPC分类号： H04N21/4305
摘要： A system and method for synchronizing a system clock in accordance with a program clock reference of a content data stream includes application of incremental delays to a local clock signal having a higher frequency than that specified by the program clock reference. The delay is made over a period defined by phase comparison between a system clock signal and a minimum delay value. Delay values are incremented proportionally to a number of clock cycles over the period. The subject system allows for display of jitter free audio or video decoded from the content data stream, and is realized in circuitry that is readily implement on an integrated circuit.
摘要翻译：根据内容数据流的节目时钟参考来同步系统时钟的系统和方法包括对具有比由节目时钟参考指定的频率更高的频率的本地时钟信号应用增量延迟。在由系统时钟信号和最小延迟值之间的相位比较定义的时间段内进行延迟。延迟值与该周期内的时钟周期数成正比地递增。主题系统允许显示从内容数据流解码的无抖动音频或视频，并且在容易在集成电路上实现的电路中实现。

7. 发明授权

US07227426B2 Using hysteresis to generate a low power clock 有权
标题翻译：使用滞后来产生低功率时钟
公开(公告)号：US07227426B2
公开(公告)日：2007-06-05
申请号：US11049420
申请日：2005-02-02
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： H03B5/32
CPC分类号： H03K19/0008 , G04F5/00
摘要： A real time clock that operates an oscillator within a predetermined range by employing a constant current source. The remaining real time clock logic can be operated at a voltage that is relative to the constant current. Power consumption of the oscillator can be controlled by limiting the current from the constant current source. The outputs of the oscillator can be input into a signal detector. A clocking signal can be produced by the signal detector based on the oscillator signals. The current provided by the first current source is limited to provide low power operation of the oscillator. Optionally, the signal detector can employ a differential amplifier. The differential amplifier receives the oscillator outputs, and provides a clocking signal based on the oscillator outputs.
摘要翻译：通过采用恒定电流源将振荡器工作在预定范围内的实时时钟。剩余的实时时钟逻辑可以在相对于恒定电流的电压下工作。可以通过限制来自恒流源的电流来控制振荡器的功耗。振荡器的输出可以输入到信号检测器中。信号检测器可以基于振荡器信号产生时钟信号。由第一电流源提供的电流被限制以提供振荡器的低功率操作。可选地，信号检测器可以采用差分放大器。差分放大器接收振荡器输出，并提供基于振荡器输出的时钟信号。

8. 发明申请

US20060170101A1 Low thermal resistance package 有权
标题翻译：低热阻包装
公开(公告)号：US20060170101A1
公开(公告)日：2006-08-03
申请号：US11049386
申请日：2005-02-02
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/3677 , H01L23/49838 , H01L2224/32225 , H01L2924/10253 , H01L2924/3011 , H01L2924/00
摘要： Techniques for arranging ball grid arrays for producing low thermal resistance packages. One embodiment is for a ball grid array package that comprises a substrate, the substrate having a top surface and a bottom surface. A plurality of thermal balls are coupled to the bottom surface of the substrate, and at least one vias is positioned between every pair of the plurality of thermal balls. Other embodiments contemplate a ball grid array comprising thermal balls with a via located between every four thermal balls, wherein at least one vias is substituted for a thermal ball in the ball grid array.
摘要翻译：用于生产低热阻包装的球栅阵列的技术。一个实施例是用于包括衬底的球栅阵列封装，该衬底具有顶表面和底表面。多个热球联接到基底的底表面，并且至少一个通孔位于每对多个热球之间。其他实施例考虑了一种球栅阵列，其包括热球，其中通孔位于每四个热球之间，其中至少一个通孔代替球栅阵列中的热球。

9. 发明授权

US07151399B2 System and method for generating multiple clock signals 有权
标题翻译：用于产生多个时钟信号的系统和方法
公开(公告)号：US07151399B2
公开(公告)日：2006-12-19
申请号：US11049442
申请日：2005-02-02
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： H03M1/12
CPC分类号： H03L7/1974 , G06F1/06
摘要： A technique for generating multiple clock signals using a frequency generator for generating a common clock signal. A first digital divider and multiplier receives the common clock signal and produces a first clock signal. A second digital divider and multiplier receives the common clock signal and produces a second clock signal, the second clock signal being at a different frequency than the first clock signal. A third digital divider and multiplier receives the common clock signal and produces a third clock signal, the third clock signal being at a different frequency than the first clock signal and the second clock signal. The common clock signal can be the greatest common measure of the first, second and third clock signals divided by a multiple of two.
摘要翻译：一种使用频率发生器产生多个时钟信号以产生公共时钟信号的技术。第一数字分频器和乘法器接收公共时钟信号并产生第一时钟信号。第二数字分频器和乘法器接收公共时钟信号并产生第二时钟信号，第二时钟信号处于与第一时钟信号不同的频率。第三数字分频器和乘法器接收公共时钟信号并产生第三时钟信号，第三时钟信号处于与第一时钟信号和第二时钟信号不同的频率。公共时钟信号可以是第一，第二和第三时钟信号除以2的倍数的最大常用度量。

10. 发明申请

US20060061428A1 Real time clock 有权
标题翻译：实时时钟
公开(公告)号：US20060061428A1
公开(公告)日：2006-03-23
申请号：US11049420
申请日：2005-02-02
申请人： Masao Kaizuka
发明人： Masao Kaizuka
IPC分类号： H03L7/099
CPC分类号： H03K19/0008 , G04F5/00
摘要： A real time clock that operates an oscillator within a predetermined range by employing a constant current source. The remaining real time clock logic can be operated at a voltage that is relative to the constant current. Power consumption of the oscillator can be controlled by limiting the current from the constant current source. The outputs of the oscillator can be input into a signal detector. A clocking signal can be produced by the signal detector based on the oscillator signals. The current provided by the first current source is limited to provide low power operation of the oscillator. Optionally, the signal detector can employ a differential amplifier. The differential amplifier receives the oscillator outputs, and provides a clocking signal based on the oscillator outputs.
摘要翻译：通过采用恒定电流源将振荡器工作在预定范围内的实时时钟。剩余的实时时钟逻辑可以在相对于恒定电流的电压下工作。可以通过限制来自恒流源的电流来控制振荡器的功耗。振荡器的输出可以输入到信号检测器中。信号检测器可以基于振荡器信号产生时钟信号。由第一电流源提供的电流被限制以提供振荡器的低功率操作。可选地，信号检测器可以采用差分放大器。差分放大器接收振荡器输出，并提供基于振荡器输出的时钟信号。

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