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1. 发明授权

US5623700A Interface circuit having zero latency buffer memory and cache memory information transfer 失效
标题翻译：接口电路具有零延迟缓冲存储器和高速缓冲存储器信息传输
公开(公告)号：US5623700A
公开(公告)日：1997-04-22
申请号：US223874
申请日：1994-04-06
申请人： Terry J. Parks , Craig S. Jones , Darius D. Gaskins
发明人： Terry J. Parks , Craig S. Jones , Darius D. Gaskins
IPC分类号： G06F12/08 , G06F13/38 , G06F13/14
CPC分类号： G06F12/0835 , G06F12/0866 , G06F13/385
摘要： A caching disk controller is provided which includes a bus bridge that forms an interface between a memory of the disk controller and a host computer. The caching disk controller further includes a SCSI processor for controlling the transfer of data from a SCSI disk drive to the memory via a local bus. A zero latency DMA controller embodied within the bus bridge snoops the local bus as data is being transferred from the SCSI disk drive to the memory, and thereby allows the data to be sequentially latched within a data FIFO of the bus bridge concurrently with its transfer into the memory. As a result, the requested data may be advantageously provided from the bus bridge to the host computer with reduced delay, while the data continues to be stored within the memory to accommodate high hit rates during subsequent transfers.
摘要翻译：提供了一种缓存磁盘控制器，其包括形成磁盘控制器的存储器和主计算机之间的接口的总线桥。缓存磁盘控制器还包括SCSI处理器，用于经由本地总线控制从SCSI磁盘驱动器传送到存储器的数据。当数据正在从SCSI磁盘驱动器传输到存储器时，总线桥中实现的零延迟DMA控制器会窥探本地总线，从而允许数据在总线桥的数据FIFO中顺序锁存，同时传输到记忆。结果，可以有利地从所述总线桥提供所请求的数据到具有减小的延迟的主计算机，同时数据继续存储在存储器内以在后续传送期间适应高命中率。

2. 发明授权

US5862369A Method and apparatus for state machine optimization using device delay characteristics 失效
标题翻译：使用设备延迟特性进行状态机优化的方法和装置
公开(公告)号：US5862369A
公开(公告)日：1999-01-19
申请号：US709239
申请日：1996-09-03
申请人： Terry J. Parks , Darius D. Gaskins
发明人： Terry J. Parks , Darius D. Gaskins
IPC分类号： H03K5/00 , H03K5/135 , G06F1/04
CPC分类号： H03K5/135 , H03K2005/00104
摘要： A method and apparatus which enables circuitry to detect and take advantage of the intrinsic performance or delay characteristic of the respective device in which the circuitry is embedded. By determining the delay characteristics of the device and sampling signals based on this information, the circuitry may not be required to wait for additional clock cycles which is required for logic in prior art devices which do not take advantage of the device's intrinsic performance. This considerably increases device performance. A device delay encoder circuit included in a device encodes the instantaneous delay coefficient of the device in question and a clocking signal is used to determine whether the delay elements should be considered fast or slow. All of the logic circuitry on a chip have a similar derating factor, and thus the performance of the delay elements is indicative of the performance of the entire chip. The encoded device delay information is then used by logic circuitry in the respective device on that cycle to determine when to sample Therefore, where a respective device has a small delay coefficient, and the device includes logic according to the present invention, the device can perform operations in a reduced number of clock cycles. This significantly increases device performance.
摘要翻译：一种方法和装置，其使得电路能够检测并利用嵌入电路的相应装置的固有性能或延迟特性。通过基于该信息确定器件的延迟特性和采样信号，可能不需要电路等待不利用器件的内在性能的现有技术器件中逻辑所需的额外时钟周期。这大大增加了设备性能。包括在设备中的设备延迟编码器电路对所述设备的瞬时延迟系数进行编码，并且使用时钟信号来确定延迟元件是否应被认为是快速或慢速的。芯片上的所有逻辑电路具有相似的降额因子，因此延迟元件的性能表示整个芯片的性能。编码的设备延迟信息然后由该周期的相应设备中的逻辑电路使用，以确定何时采样因此，在相应设备具有小的延迟系数的情况下，并且该设备包括根据本发明的逻辑，该设备可以执行减少时钟周期的操作。这显着提高了设备性能。

3. 发明授权

US5708794A Multi-purpose usage of transaction backoff and bus architecture supporting same 失效
标题翻译：多用途交易回退和总线架构支持相同
公开(公告)号：US5708794A
公开(公告)日：1998-01-13
申请号：US692326
申请日：1996-08-05
申请人： Terry J. Parks , Darius D. Gaskins , Charles Zeller
发明人： Terry J. Parks , Darius D. Gaskins , Charles Zeller
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4036
摘要： A digital processor system is disclosed that employs a bus bridge interfacing a primary bus to a secondary bus and which includes a transaction backoff signal line that provides an economical method of providing split transactions between the busses, of preventing deadlock situations between the busses, and of providing strong lock ordering across the busses. A primary bus master is backed-off the bus if it is attempting to access a device resident on the secondary bus and if mastership of the secondary bus cannot be attained by the bus bridge within a certain latency. The bus bridge further implements a method of prefetching read data from a device resident on the secondary bus in response to a primary bus master being backed-off the primary bus during a read operation.
摘要翻译：公开了一种数字处理器系统，其采用将主总线连接到辅助总线的总线桥，其包括交易回退信号线，其提供在总线之间提供分离交易的经济方法，以防止总线之间的死锁情况，以及在整个公共汽车上提供强大的锁定顺序。如果主总线主机试图访问辅助总线上的设备，并且如果在一定的延迟期间总线桥不能实现辅助总线的主控，则总线总线将被退出总线。总线桥接器进一步实现了一种从读取操作期间响应于主总线主机被退出主总线的驻留在辅助总线上的设备预读取数据的方法。

4. 发明授权

US5517671A System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus 失效
标题翻译：用于将多个I / O设备指定到多个I / O通道并将多个I / O通道连接和缓冲到单个系统总线的系统
公开(公告)号：US5517671A
公开(公告)日：1996-05-14
申请号：US100714
申请日：1993-07-30
申请人： Terry J. Parks , Darius D. Gaskins
发明人： Terry J. Parks , Darius D. Gaskins
IPC分类号： G06F13/364 , G06F13/40 , G06F13/00 , G06F13/14 , G06F13/20
CPC分类号： G06F13/364 , G06F13/4031 , G06F13/4059
摘要： A system for connecting a plurality of input/output (I/O) channels to a single computer system bus. A system controller establishes priority among the I/O channels competing for access to the system bus. A plurality of I/O channel bridges are connected to the system bus and interface with EISA channels. The I/O bridges receive data from the EISA channels at one data rate and transmit the data to the system bus at another data rate. Data is stored within the I/O bridges in a cache memory device until commanded to transmit the data to the system bus by the system controller.
摘要翻译：用于将多个输入/输出（I / O）通道连接到单个计算机系统总线的系统。系统控制器在竞争访问系统总线的I / O通道之间建立优先级。多个I / O通道桥连接到系统总线并与EISA通道接口。 I / O桥以一个数据速率从EISA通道接收数据，并以另一数据速率将数据传输到系统总线。数据存储在高速缓存存储器中的I / O桥内，直到系统控制器命令将数据发送到系统总线为止。

5. 发明授权

US5638527A System and method for memory mapping 失效
标题翻译：内存映射的系统和方法
公开(公告)号：US5638527A
公开(公告)日：1997-06-10
申请号：US634013
申请日：1996-04-17
申请人： Terry J. Parks , Darius D. Gaskins
发明人： Terry J. Parks , Darius D. Gaskins
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/0284
摘要： A memory mapping scheme for a computer system includes a number of slave devices attached to a system bus, which slave devices have partitioned among themselves a memory address storage system. The memory address storage system is, in turn, divided into a number of regions. The memory mapping scheme also includes a subsystem for mapping the regions, which subsystem includes a unique subtractive descriptor that disjunctively allows mapping of regions that reside on only one of a number of input/output channels connected to the system bus.
摘要翻译：用于计算机系统的存储器映射方案包括附加到系统总线的多个从设备，这些从设备在它们之间划分为存储器地址存储系统。存储器地址存储系统又被分成多个区域。存储器映射方案还包括用于映射区域的子系统，该子系统包括唯一的减法描述符，其分离地允许仅驻留在连接到系统总线的多个输入/输出通道中的一个上的区域的映射。

6. 发明授权

US5384788A Apparatus and method for optimal error correcting code to parity conversion 失效
公开(公告)号：US5384788A
公开(公告)日：1995-01-24
申请号：US966235
申请日：1992-10-26
申请人： Terry J. Parks , Darius D. Gaskins
发明人： Terry J. Parks , Darius D. Gaskins
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/10
摘要： This invention relates to the general area of data integrety in digital computers. In particular it relates to digital computer systems having parity checked systems busses and ECC checked memory. This invention increases the performance of such systems by reducing the memory latency incurred in the ECC to parity conversion process.

7. 发明授权

US5640517A Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order 失效
标题翻译：用于主机命令从站的方法和装置是否以顺序或非顺序的突发顺序传送数据
公开(公告)号：US5640517A
公开(公告)日：1997-06-17
申请号：US607051
申请日：1996-02-26
申请人： Terry J. Parks , Darius D. Gaskins
发明人： Terry J. Parks , Darius D. Gaskins
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A bus with selective burst ordering enables the implementation of computer systems that incorporate bus masters (e.g., processors, DMA controllers, LAN controllers, etc.) with dissimilar burst orders. The same bus supports devices which require or prefer differing burst orders for high bandwidth data transfers. Selective burst order is enabled through the use of a bus line which may be asserted by the current bus master. By asserting the corresponding signal, a current bus master indicates that sequential (rather than non-sequential) burst order will be used for data transfer. Specialized burst address generation logic enables a bus slave to generate, in the selected burst order, the low order bits of memory addresses for the data words implicitly addressed during a burst transfer.
摘要翻译：具有选择性突发排序的总线使得能够实现具有不同突发命令的总线主机（例如，处理器，DMA控制器，LAN控制器等）的计算机系统。相同的总线支持需要或更喜欢用于高带宽数据传输的不同突发命令的设备。选择性突发命令通过使用可由当前总线主机断言的总线启用。通过断言相应的信号，当前总线主机指示顺序（而不是非顺序）突发顺序将用于数据传输。专用脉冲串地址生成逻辑使总线从站能够以突发顺序生成在突发传输期间隐含寻址的数据字的存储器地址的低位位。

8. 发明授权

US5590338A Combined multiprocessor interrupt controller and interprocessor communication mechanism 失效
标题翻译：组合多处理器中断控制器和处理器间通信机制
公开(公告)号：US5590338A
公开(公告)日：1996-12-31
申请号：US512867
申请日：1995-08-08
申请人： Terry J. Parks , Darius D. Gaskins
发明人： Terry J. Parks , Darius D. Gaskins
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A combined multiprocessor interrupt controller and interprocessor communication mechanism includes a system bus, an input/output bridge element coupled to the system bus, and a system controller coupled to the system bus. The input/output bridge element includes circuitry for receiving interrupt requests, for obtaining processor-associated vectors, and for packaging obtained processor-associated vectors into interprocessor communication messages. The system controller includes circuitry for receiving and decoding interprocessor communication messages, and for providing processor-associated vectors to the associated processor.
摘要翻译：组合的多处理器中断控制器和处理器间通信机制包括系统总线，耦合到系统总线的输入/输出桥接元件以及耦合到系统总线的系统控制器。输入/输出桥元件包括用于接收中断请求的电路，用于获得处理器相关联的向量，以及将获得的处理器相关向量封装到处理器间通信消息中。系统控制器包括用于接收和解码处理器间通信消息的电路，以及用于向相关处理器提供处理器相关向量。

9. 发明授权

US5465346A Method and apparatus for synchronous bus interface optimization 失效
标题翻译：同步总线接口优化方法和装置
公开(公告)号：US5465346A
公开(公告)日：1995-11-07
申请号：US102446
申请日：1993-08-05
申请人： Terry J. Parks , Darius D. Gaskins
发明人： Terry J. Parks , Darius D. Gaskins
IPC分类号： H03K5/00 , H03K5/135 , G06F13/00 , G06F13/36
CPC分类号： H03K5/135 , H03K2005/00104
摘要： A method and apparatus which enables devices connected to a bus to detect and take advantage of the early arrival of bus signal inputs. A signal arrival encoder circuit included in a device encodes the arrival time of a signal input whose early arrival is desired to be detected. The arrival time of the signal at issue is categorized according to a desired degree of precision or granularity depending upon the complexity of the encoder used in the respective embodiment. The encoded signal arrival information is then used by the respective device to determine when to sample the other respective input signal. By detecting the early arrival of this input, the device is not required to wait for the worst case signal arrival time to utilize the information. This considerably increases system performance.
摘要翻译：连接到总线的设备能够检测并利用总线信号输入的早期到达的方法和装置。设备中包括的信号到达编码器电路对希望早期到达的信号输入的到达时间进行编码。根据各个实施例中使用的编码器的复杂度，根据期望的精度或粒度来分类问题信号的到达时间。编码的信号到达信息然后由相应的装置使用，以确定何时采样另一个相应的输入信号。通过检测该输入的早期到达，该装置不需要等待最坏情况信号到达时间来利用该信息。这大大提高了系统性能。

10. 发明授权

US5357622A Apparatus for queing and storing data writes into valid word patterns 失效
标题翻译：用于排队和存储数据的设备写入有效的字模式
公开(公告)号：US5357622A
公开(公告)日：1994-10-18
申请号：US589341
申请日：1990-09-27
申请人： Terry J. Parks , Darius D. Gaskins , Michael L. Longwell , Keith D. Matteson
发明人： Terry J. Parks , Darius D. Gaskins , Michael L. Longwell , Keith D. Matteson
IPC分类号： G06F5/00 , G06F11/10 , G06F12/00
CPC分类号： G06F5/00 , G06F11/1008
摘要： A digital computer system has a central processor unit (CPU) and a store queue facility. The store queue facility receives full digital words or segments thereof (bytes) for intermediate storage prior to storage in an addressable unit such as a dynamic random access memory (DRAM). The store queue facility has a plurality of registers for storing digital words and bytes for storage at different, discreet addresses in the addressable unit. The store queue has circuitry for assembling bytes into a digital word or into a plurality of bytes for ultimate storage in the addressable unit. Some combinations of bytes are not valid and will therefore not be entered together in a single digital word.
摘要翻译：数字计算机系统具有中央处理器单元（CPU）和存储队列设施。存储队列设施在存储在诸如动态随机存取存储器（DRAM）的可寻址单元之前接收用于中间存储的全数字字或其段（字节）。存储队列设施具有多个用于存储数字字和字节的寄存器，用于存储在可寻址单元中的不同的，谨慎的地址处。存储队列具有用于将字节组合成数字字或多个字节的电路，用于可寻址单元中的最终存储。字节的某些组合是无效的，因此不能一起输入到单个数字字中。

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