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1. 发明授权

US06790125B2 Backside integrated circuit die surface finishing technique and tool 有权
标题翻译：背面集成电路模具表面处理技术和工具
公开(公告)号：US06790125B2
公开(公告)日：2004-09-14
申请号：US09734225
申请日：2000-12-11
申请人： Terence Kane , Darrell L. Miles
发明人： Terence Kane , Darrell L. Miles
IPC分类号： B24B100
CPC分类号： B24B37/04 , B24B49/16
摘要： A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.
摘要翻译：制备用于分析的半导体管芯的方法包括：提供一半导体管芯，该半导体管芯具有在一侧的连接器和相对的待分析背面，提供用于抛光半导体管芯的背面的抛光垫，提供用于固定的可旋转主轴抛光垫，并且在主轴上提供恒定的力致动器，恒力致动器适于在抛光垫和模具的后侧表面之间提供恒定的力。该方法然后包括使背面模具表面与抛光垫接触，旋转主轴和抛光垫，并且用恒定力致动器保持抛光垫在模具背面上的基本上恒定的力，抛光模具的背面。

2. 发明授权

US06852629B2 Backside integrated circuit die surface finishing technique and tool 失效
标题翻译：背面集成电路模具表面处理技术和工具
公开(公告)号：US06852629B2
公开(公告)日：2005-02-08
申请号：US10751758
申请日：2004-01-05
申请人： Terence Kane , Darrell L. Miles
发明人： Terence Kane , Darrell L. Miles
IPC分类号： B24B37/04 , B24B49/16 , H01L21/302 , H01L21/461
CPC分类号： B24B37/04 , B24B49/16
摘要： A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.
摘要翻译：制备用于分析的半导体管芯的方法包括：提供一半导体管芯，该半导体管芯具有在一侧的连接器和相对的待分析背面，提供用于抛光半导体管芯的背面的抛光垫，提供用于固定的可旋转主轴抛光垫，并且在主轴上提供恒定的力致动器，恒力致动器适于在抛光垫和模具的后侧表面之间提供恒定的力。该方法然后包括使背面模具表面与抛光垫接触，旋转主轴和抛光垫，并且用恒定力致动器保持抛光垫在模具背面上的基本上恒定的力，抛光模具的背面。

3. 发明授权

US06894522B2 Specific site backside underlaying and micromasking method for electrical characterization of semiconductor devices 失效
标题翻译：半导体器件的电气特性的具体现场背面底层和微掩模方法
公开(公告)号：US06894522B2
公开(公告)日：2005-05-17
申请号：US10605530
申请日：2003-10-06
申请人： Barbara A. Averill , Terence Kane , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri
发明人： Barbara A. Averill , Terence Kane , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri
IPC分类号： G01N1/32 , G01R31/28 , G01R31/26
CPC分类号： G01R31/2886 , G01N1/32 , G01R31/2898
摘要： A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.
摘要翻译：用于实现半导体器件的背面探测的方法包括隔离半导体器件的背面上的识别的缺陷区域，以及将所识别的缺陷区域研磨到初始深度。所识别的缺陷区域的边缘被掩蔽，其中从初始深度开始的未屏蔽半导体材料被蚀刻多个定时间隔，直到达到一个或多个有源器件。一个或多个有源器件被电探测。

4. 发明授权

US07112983B2 Apparatus and method for single die backside probing of semiconductor devices 有权
标题翻译：半导体器件单模背面探测的装置和方法
公开(公告)号：US07112983B2
公开(公告)日：2006-09-26
申请号：US10904435
申请日：2004-11-10
申请人： Patrick J. McGinnis , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri , Manuel J. Villalobos
发明人： Patrick J. McGinnis , Darrell L. Miles , Richard W. Oldrey , John D. Sylvestri , Manuel J. Villalobos
IPC分类号： G01R31/26
CPC分类号： G01R31/2886 , G01R1/0408 , G01R31/311
摘要： An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.
摘要翻译：用于促进半导体器件的单模背面探测的装置包括芯片保持器，其构造成用于接收附接到其上的单个集成电路管芯，所述芯片保持器相对于升降板以X-Y取向保持柔性接合。提升环联接到提升板，提升环构造成便于在Z方向上调节提升板和芯片保持器。

5. 发明授权

US07826045B2 Angular spectrum tailoring in solid immersion microscopy for circuit analysis 失效
标题翻译：用于电路分析的固体浸液显微镜中的角度光谱裁剪
公开(公告)号：US07826045B2
公开(公告)日：2010-11-02
申请号：US12020157
申请日：2008-01-25
申请人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
发明人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
IPC分类号： G01N21/00
CPC分类号： G01R31/311
摘要： A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译：一种用于定位半导体芯片中的故障的方法和结构。芯片包括电介质互连上的衬底。包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。

6. 发明授权

US07993504B2 Backside unlayering of MOSFET devices for electrical and physical characterization 有权
标题翻译：用于电气和物理表征的MOSFET器件的背面非层叠
公开(公告)号：US07993504B2
公开(公告)日：2011-08-09
申请号：US12027563
申请日：2008-02-07
申请人： Terence L. Kane , Darrell L. Miles , John D. Sylvestri , Michael P. Tenney
发明人： Terence L. Kane , Darrell L. Miles , John D. Sylvestri , Michael P. Tenney
IPC分类号： C23C14/34
CPC分类号： H01J37/32366 , G01N1/32 , G01R31/2898 , H01J2237/3114
摘要： A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
摘要翻译：一种用于背面非层叠半导体器件以暴露设备的FEOL半导体特征以用于随后的电和/或物理探测的方法和系统。在半导体的背面基板层内形成窗口。产生并引导准直离子等离子体，以便仅通过聚焦屏蔽件中的开口在后侧窗口内接触半导体。这种聚焦的准直离子等离子体仅在窗口内接触半导体，同时半导体同时被温度控制的阶段旋转和倾斜，以均匀地去除半导体层，使得半导体特征在半导体上对应于后视窗，曝光。通过CAIBE处理可以增强本发明的背面未铺层。

7. 发明申请

US20080128086A1 BACKSIDE UNLAYERING OF MOSFET DEVICES FOR ELECTRICAL AND PHYSICAL CHARACTERIZATION 有权
标题翻译：用于电气和物理特性的MOSFET器件的背面分布
公开(公告)号：US20080128086A1
公开(公告)日：2008-06-05
申请号：US12027563
申请日：2008-02-07
申请人： Terence L. Kane , Darrell L. Miles , John D. Sylvestri , Michael P. Tenney
发明人： Terence L. Kane , Darrell L. Miles , John D. Sylvestri , Michael P. Tenney
IPC分类号： H01L21/306
CPC分类号： H01J37/32366 , G01N1/32 , G01R31/2898 , H01J2237/3114
摘要： A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
摘要翻译：一种用于背面非层叠半导体器件以暴露设备的FEOL半导体特征以用于随后的电和/或物理探测的方法和系统。在半导体的背面基板层内形成窗口。产生并引导准直离子等离子体，以便仅通过聚焦屏蔽件中的开口在后侧窗口内接触半导体。这种聚焦的准直离子等离子体仅在窗口内接触半导体，同时半导体同时被温度控制的阶段旋转和倾斜，以均匀地去除半导体层，使得半导体特征在半导体上对应于后视窗，曝光。通过CAIBE处理可以增强本发明的背面未铺层。

8. 发明申请

US20110037973A1 ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS 失效
标题翻译：用于电路分析的固体显微镜中的角度光谱定标
公开(公告)号：US20110037973A1
公开(公告)日：2011-02-17
申请号：US12911781
申请日：2010-10-26
申请人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
发明人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
IPC分类号： G01N21/88
CPC分类号： G01R31/311
摘要： A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译：用于定位半导体芯片中的故障的结构。芯片包括电介质互连上的衬底。包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。

9. 发明授权

US07015146B2 Method of processing backside unlayering of MOSFET devices for electrical and physical characterization including a collimated ion plasma 失效
标题翻译：处理用于包括准直离子等离子体的电和物理表征的MOSFET器件的背面非层叠的方法
公开(公告)号：US07015146B2
公开(公告)日：2006-03-21
申请号：US10752162
申请日：2004-01-06
申请人： Terence L. Kane , Darrell L. Miles , John D. Sylyestri , Michael P. Tenney
发明人： Terence L. Kane , Darrell L. Miles , John D. Sylyestri , Michael P. Tenney
IPC分类号： H01L21/302 , H01L21/462 , A61N5/00 , G21G5/00 , C23F1/00
CPC分类号： H01J37/32366 , G01N1/32 , G01R31/2898 , H01J2237/3114
摘要： A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
摘要翻译：一种用于背面非层叠半导体器件以暴露设备的FEOL半导体特征以用于随后的电和/或物理探测的方法和系统。在半导体的背面基板层内形成窗口。产生并引导准直离子等离子体，以便仅通过聚焦屏蔽件中的开口在后侧窗口内接触半导体。这种聚焦的准直离子等离子体仅在窗口内接触半导体，同时半导体同时被温度控制的阶段旋转和倾斜，以均匀地去除半导体层，使得半导体特征在半导体上对应于后视窗，曝光。通过CAIBE处理可以增强本发明的背面未铺层。

10. 发明授权

US07961307B2 Angular spectrum tailoring in solid immersion microscopy for circuit analysis 失效
标题翻译：用于电路分析的固体浸液显微镜中的角度光谱裁剪
公开(公告)号：US07961307B2
公开(公告)日：2011-06-14
申请号：US12911781
申请日：2010-10-26
申请人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
发明人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
IPC分类号： G01N21/00
CPC分类号： G01R31/311
摘要： A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译：用于定位半导体芯片中的故障的结构。芯片包括电介质互连上的衬底。包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。

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