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1. 发明申请

US20090031170A1 System and method to facilitate automatic globalization verification test 有权
标题翻译：系统和方法方便自动全球化验证测试
公开(公告)号：US20090031170A1
公开(公告)日：2009-01-29
申请号：US11828459
申请日：2007-07-26
申请人： Teppei Tsurumi , Yu Wang , John F. Sefler , Jeff Weiss , Morgan Johnson , Al Chakra
发明人： Teppei Tsurumi , Yu Wang , John F. Sefler , Jeff Weiss , Morgan Johnson , Al Chakra
IPC分类号： G06F11/36
CPC分类号： G06F11/3696 , G06F11/3692
摘要： A method, system and program are disclosed for validating the generation of globalized versions of software programs. The directory structure of an installed software program is traversed to discover resource files containing globalized strings. The values of the globalized string and its corresponding key in the resource file are then used to generate a unique key, formatted to identify the location of the globalized string. The locale supported by the globalized string is determined and the unique key and the globalized string value are appended to a corresponding locale table. A globalized string value that causes the failure of a globalization test for a predetermined locale is identified. The corresponding locale table is then searched for the failed globalized string value. Once found, the unique key for the failed globalized string value is retrieved to identify the location of the defective globalized string and perform predetermined remedial actions.
摘要翻译：公开了用于验证软件程序的全球化版本的生成的方法，系统和程序。遍历安装的软件程序的目录结构以发现包含全球化字符串的资源文件。然后，全局化字符串的值和资源文件中的对应关键字用于生成唯一的密钥，用于标识全局化字符串的位置。确定全局化字符串支持的语言环境，并将唯一键和全局化字符串值附加到相应的语言环境表。识别出导致全局测试失败的全局化字符串值对于预定区域。然后搜索相应的语言环境表以获取失败的全局化字符串值。一旦找到，检索失败的全球化字符串值的唯一键，以识别缺陷全局化字符串的位置，并执行预定的补救措施。

2. 发明授权

US07793156B2 System and method to facilitate automatic globalization verification test 有权
标题翻译：系统和方法方便自动全球化验证测试
公开(公告)号：US07793156B2
公开(公告)日：2010-09-07
申请号：US11828459
申请日：2007-07-26
申请人： Teppei Tsurumi , Yu Wang , John F. Sefler , Jeff Weiss , Morgan Johnson , Al Chakra
发明人： Teppei Tsurumi , Yu Wang , John F. Sefler , Jeff Weiss , Morgan Johnson , Al Chakra
IPC分类号： G06F11/00
CPC分类号： G06F11/3696 , G06F11/3692
摘要： A method, system and program are disclosed for validating the generation of globalized versions of software programs. The directory structure of an installed software program is traversed to discover resource files containing globalized strings. The values of the globalized string and its corresponding key in the resource file are then used to generate a unique key, formatted to identify the location of the globalized string. The locale supported by the globalized string is determined and the unique key and the globalized string value are appended to a corresponding locale table. A globalized string value that causes the failure of a globalization test for a predetermined locale is identified. The corresponding locale table is then searched for the failed globalized string value. Once found, the unique key for the failed globalized string value is retrieved to identify the location of the defective globalized string and perform predetermined remedial actions.
摘要翻译：公开了用于验证软件程序的全球化版本的生成的方法，系统和程序。遍历安装的软件程序的目录结构以发现包含全球化字符串的资源文件。然后，全局化字符串的值和资源文件中的对应关键字用于生成唯一的密钥，用于标识全局化字符串的位置。确定全局化字符串支持的语言环境，并将唯一键和全局化字符串值附加到相应的语言环境表。识别出导致全局测试失败的全局化字符串值对于预定区域。然后搜索相应的语言环境表以获取失败的全局化字符串值。一旦找到，检索失败的全球化字符串值的唯一键，以识别缺陷全局化字符串的位置，并执行预定的补救措施。

3. 发明申请

US20050194353A1 Laser micromachining and electrical structures formed thereby 审中-公开
公开(公告)号：US20050194353A1
公开(公告)日：2005-09-08
申请号：US11104985
申请日：2005-04-11
申请人： Morgan Johnson , William Miller
发明人： Morgan Johnson , William Miller
IPC分类号： B23K26/073 , B23K26/38 , H05K1/00 , H05K1/02 , H05K1/16 , H05K3/00 , H05K3/02 , C23F1/00 , B44C1/22 , C03C15/00
CPC分类号： B23K26/073 , B23K26/382 , B23K26/40 , B23K2101/40 , B23K2103/12 , B23K2103/172 , B23K2103/42 , B23K2103/50 , H05K1/0269 , H05K1/0393 , H05K1/165 , H05K3/0032 , H05K3/0052 , H05K3/027 , H05K2201/09063 , H05K2201/0909 , H05K2201/09918
摘要： A unified process of making an electrical structure includes performing a plurality of laser etching operations on a workpiece, without removing the workpiece from a laser processing system. The workpiece includes a conductive material disposed on an electrically insulating substrate, and the plurality of laser etching operations include, but are not limited to, two or more of forming a fiducial, forming thick metal traces separated by high aspect ratio spaces, cutting an alignment hole, cutting a folding line, and singulating the electrical structure. In another aspect of the invention, a database is prepared, and communicatively coupled to the laser processing system to provide control signals that direct a portion of the plurality of operations of the laser processing system, wherein each plurality of etching operations is defined with respect to a common coordinate system.

4. 发明授权

US4700214A Electrical circuitry 失效
标题翻译：电路
公开(公告)号：US4700214A
公开(公告)日：1987-10-13
申请号：US53607
申请日：1987-05-20
申请人： Morgan Johnson
发明人： Morgan Johnson
IPC分类号： H01L23/538 , H05K1/00 , H05K1/11 , H05K3/00 , H05K3/30 , H05K3/32 , H05K3/40 , H05K3/46 , H05K3/08
CPC分类号： H05K3/326 , H01L23/5382 , H05K1/0287 , H01L2924/0002 , H05K1/118 , H05K2201/091 , H05K2201/10303 , H05K2201/1059 , H05K2203/175 , H05K3/0058 , H05K3/306 , H05K3/4046 , H05K3/4611
摘要： Electrical circuitry 32 is comprised of a plurality of layers 30, 100, each layer 30, 100 including one or more electrical pathways 36, 38, each layer 30, 100 also including insulation 34 for insulating at least part of one layer 30 from another layer 100. The pathways 36, 38 comprise repeating patterns 40, 42. Each pathway 36, 38 of each layer 30, 100 can communicate with the pathways 36, 38 of the next adjacent layers 30, 100. Some portions of the patterns 40, 42 which comprise the pathways 36, 38 of each layer 30, 100 can be at least partially aligned with some portion of the patterns 40, 42 of pathways 36, 38 of the other layers 30, 100. Other portions of the pathways 36, 38 of the layers 30, 100 remain unaligned. A pulse laser 134 can be used to sever unaligned portions of the pathways 36, 38 as appropriate to create the desired electrical circuitry 32. Components can be secured to the electrical circuitry as required. Further, such circuitry can be used in the construction of the final metallization layers of chips such as gate arrays.
摘要翻译：电路32由多个层30,100组成，每个层30,100包括一个或多个电通路36,38，每个层30,100还包括绝缘层34，用于将一层30的至少一部分与另一层路径36,38包括重复图案40,42。每个层30,100的每个路径36,38可以与下一相邻层30,100的路径36,38连通。图案40,42的某些部分其包括每个层30,100的通路36,38可以至少部分地与其它层30,100的通路36,38的图案40,42的一些部分对准。通路36,38的其他部分层30,100保持不对齐。可以使用脉冲激光器134来适当地切断通路36,38的未对准部分以产生所需的电路32.组件可以根据需要固定到电路。此外，这种电路可用于构建诸如门阵列的芯片的最终金属化层。

5. 发明授权

US08908384B2 Motherboard substrate having no memory interconnects 有权
标题翻译：没有存储器互连的主板基板
公开(公告)号：US08908384B2
公开(公告)日：2014-12-09
申请号：US13491378
申请日：2012-06-07
申请人： Morgan Johnson , Frederick G. Weiss
发明人： Morgan Johnson , Frederick G. Weiss
IPC分类号： H05K7/00 , H05K1/02 , H01L23/32 , G06F1/32 , H05K1/18 , H05K1/14
CPC分类号： G06F13/16 , G06F1/32 , G06F13/4068 , G11C5/04 , H01L23/32 , H01L23/49838 , H01L23/4985 , H01L2924/0002 , H05K1/0237 , H05K1/0243 , H05K1/0296 , H05K1/111 , H05K1/115 , H05K1/141 , H05K1/147 , H05K1/181 , H05K1/189 , H05K2201/095 , H05K2201/10159 , H05K2201/10189 , H05K2201/10378 , H05K2201/10515 , H05K2201/10522 , Y02D10/151 , Y10T29/4913 , H01L2924/00
摘要： A computing device has a motherboard circuit substrate having at least one layer of electrical interconnects and a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the layer of electrical interconnects, wherein the circuit substrate has no memory interconnects.
摘要翻译：计算设备具有具有至少一层电互连层的母板电路基板和布置成接收用于计算设备的主处理器的插座，该插座电耦合到电互连层的至少一部分，其中电路基板没有内存互连。

6. 发明授权

US08363418B2 Above motherboard interposer with peripheral circuits 有权
标题翻译：以上主板插入器与外围电路
公开(公告)号：US08363418B2
公开(公告)日：2013-01-29
申请号：US13163502
申请日：2011-06-17
申请人： Morgan Johnson , Frederick G. Weiss
发明人： Morgan Johnson , Frederick G. Weiss
IPC分类号： H05K7/00
CPC分类号： G06F13/16 , G06F1/32 , G06F13/4068 , G11C5/04 , H01L23/32 , H01L23/49838 , H01L23/4985 , H01L2924/0002 , H05K1/0237 , H05K1/0243 , H05K1/0296 , H05K1/111 , H05K1/115 , H05K1/141 , H05K1/147 , H05K1/181 , H05K1/189 , H05K2201/095 , H05K2201/10159 , H05K2201/10189 , H05K2201/10378 , H05K2201/10515 , H05K2201/10522 , Y02D10/151 , Y10T29/4913 , H01L2924/00
摘要： An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.
摘要翻译：插入器衬底包括插入器衬底中的互连阵列，所述连接器阵列根据用于电路衬底上的处理器的互连阵列布置，所述插入器衬底中的至少一个导电迹线与至少一个连接器所述互连阵列，所述导电迹线平行于所述插入器基板布置，使得在所述插入器基板中的所述连接器与所述电路基板上的所述处理器的相应的一个互连件之间不存在电连接;以及至少一个外围电路，所述插入器衬底与所述导电迹线电连接。

7. 发明申请

US20120300392A1 HEAT MANAGEMENT IN AN ABOVE MOTHERBOARD INTERPOSER WITH PERIPHERAL CIRCUITS 审中-公开
标题翻译：具有外围电路的上述主机插座的热管理
公开(公告)号：US20120300392A1
公开(公告)日：2012-11-29
申请号：US13491418
申请日：2012-06-07
申请人： Morgan Johnson , Frederick G. Weiss
发明人： Morgan Johnson , Frederick G. Weiss
IPC分类号： G06F1/20
摘要： A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, at least one peripheral circuit on the interposer substrate, and a heat sink thermally coupled to the peripheral circuit.
摘要翻译：计算装置具有电路基板，具有插座，主处理器插入插座中，插入插座和主处理器之间的插入基板，电路基板，插座和插入器基板电连接，至少一个外围电路在内插器基板上，以及热耦合到外围电路的散热器。

8. 发明申请

US20120262875A1 ABOVE MOTHERBOARD INTERPOSER WITH PERIPHERAL CIRCUITS 有权
标题翻译：上面带有外围电路的主板插座
公开(公告)号：US20120262875A1
公开(公告)日：2012-10-18
申请号：US13163502
申请日：2011-06-17
申请人： Morgan Johnson , Frederick G. Weiss
发明人： Morgan Johnson , Frederick G. Weiss
IPC分类号： G06F1/16 , G06F1/20
CPC分类号： G06F13/16 , G06F1/32 , G06F13/4068 , G11C5/04 , H01L23/32 , H01L23/49838 , H01L23/4985 , H01L2924/0002 , H05K1/0237 , H05K1/0243 , H05K1/0296 , H05K1/111 , H05K1/115 , H05K1/141 , H05K1/147 , H05K1/181 , H05K1/189 , H05K2201/095 , H05K2201/10159 , H05K2201/10189 , H05K2201/10378 , H05K2201/10515 , H05K2201/10522 , Y02D10/151 , Y10T29/4913 , H01L2924/00
摘要： An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.
摘要翻译：插入器衬底包括插入器衬底中的互连阵列，所述连接器阵列根据用于电路衬底上的处理器的互连阵列布置，所述插入器衬底中的至少一个导电迹线与至少一个连接器所述互连阵列，所述导电迹线平行于所述插入器基板布置，使得在所述插入器基板中的所述连接器与所述电路基板上的所述处理器的相应的一个互连件之间不存在电连接;以及至少一个外围电路，所述插入器衬底与所述导电迹线电连接。

9. 发明授权

US07875826B2 Variable width conductive lines having substantially constant impedance 失效
标题翻译：具有基本恒定阻抗的可变宽度导线
公开(公告)号：US07875826B2
公开(公告)日：2011-01-25
申请号：US11748257
申请日：2007-05-14
申请人： William A. Miller , Morgan Johnson
发明人： William A. Miller , Morgan Johnson
IPC分类号： B23K26/00
CPC分类号： H05K3/027 , H05K1/0245 , H05K1/025 , H05K2201/09363 , H05K2201/09727 , H05K2203/1476
摘要： A method of fabricating a conductive line provides a substrate having a blanket layer of conductive material disposed thereon, a removing of a first portion of the blanket layer of conductive material to form one or more gaps that define a first line, the gaps adjacent to the first line, the first line having at least a first segment of a first width and a second segment of a second width, the first and second widths being different, a first increasing of the width of a first gap of the one or more gaps, the first gap adjacent to the first segment, by a first amount, and a second increasing of the width of a second gap of the one or more gaps, the second gap adjacent to the second segment, by a second amount wherein the first and second increasing depend upon a desired electrical characteristic. The first amount and the second amount may be different from each other.
摘要翻译：一种制造导电线的方法提供了一种具有布置在其上的导电材料的覆盖层的衬底，去除导电材料的覆盖层的第一部分以形成限定第一线的一个或多个间隙，第一行，第一行具有至少第一宽度的第一段和第二宽度的第二段，第一和第二宽度不同，第一间隙的宽度的第一增加，与第一段相邻的第一间隙，第一数量，以及与第二段相邻的一个或多个间隙的第二间隙的第二间隙的宽度的第二增加第二数量，其中第一和第二间隙增加取决于所需的电特性。第一量和第二量可以彼此不同。

10. 发明申请

US20080003819A1 Laser isolation of metal over alumina underlayer and structures formed thereby 审中-公开
标题翻译：激光隔离氧化铝底层上的金属和由此形成的结构
公开(公告)号：US20080003819A1
公开(公告)日：2008-01-03
申请号：US11811880
申请日：2007-06-11
申请人： Morgan Johnson , James Fitzgerald
发明人： Morgan Johnson , James Fitzgerald
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/76829 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A method of reducing or eliminating electrical shorts in a metal layer when producing laser patterned metal disposed on an intermediate layer that is disposed on a substrate, such as for example, a silicon wafer, includes forming the intermediate layer from a material wherein the difference between the coefficient of thermal expansion of the intermediate layer and the coefficient of thermal expansion of the metal is less than the difference between the coefficient of thermal expansion of silicon dioxide and the coefficient of thermal expansion of aluminum. In one embodiment, a layer of alumina is deposited on a silicon wafer, a layer of aluminum is deposited on the alumina, and at least portions of the aluminum are removed by laser etching to produce one or more electrically separated structures from the aluminum layer.
摘要翻译：当制造布置在设置在诸如硅晶片的基板上的中间层上的激光图案化金属时，减少或消除金属层中的电短路的方法包括由材料形成中间层，中间层的热膨胀系数和金属的热膨胀系数小于二氧化硅的热膨胀系数与铝的热膨胀系数之差。在一个实施例中，氧化铝层沉积在硅晶片上，铝层沉积在氧化铝上，并且通过激光蚀刻去除铝的至少一部分，以从铝层产生一个或多个电分离的结构。

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