专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06638830B1 Method for fabricating a high-density capacitor 有权
标题翻译：高密度电容器制造方法
公开(公告)号：US06638830B1
公开(公告)日：2003-10-28
申请号：US10065104
申请日：2002-09-18
申请人： Teng-Chun Tsai , Chia-Lin Hsu , Yi-Fang Cheng
发明人： Teng-Chun Tsai , Chia-Lin Hsu , Yi-Fang Cheng
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L21/31604 , H01L21/3162 , H01L23/5223 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a high-density capacitor. At least one first trench is formed in a dielectric layer positioned on a semiconductor substrate. A first liner layer and a first conductive layer are formed on the semiconductor substrate followed by a first planarization process. At least one second trench having a joint side wall with the first trench is formed in the dielectric layer. A capacitor dielectric layer, a second liner layer, and a second conductive layer are formed on the semiconductor substrate followed by a second planarization process. The surfaces of the first conductive layer and the second conductive layer are then exposed to form a high-density capacitor having a three-dimensional structure.
摘要翻译：一种制造高密度电容器的方法。至少一个第一沟槽形成在位于半导体衬底上的电介质层中。在半导体衬底上形成第一衬里层和第一导电层，接着进行第一平面化处理。在电介质层中形成具有与第一沟槽的接合侧壁的至少一个第二沟槽。在半导体衬底上形成电容器电介质层，第二衬垫层和第二导电层，接着进行第二平面化处理。然后将第一导电层和第二导电层的表面暴露以形成具有三维结构的高密度电容器。

2. 发明授权

US06593185B1 Method of forming embedded capacitor structure applied to logic integrated circuit 有权
标题翻译：形成嵌入式电容器结构的方法应用于逻辑集成电路
公开(公告)号：US06593185B1
公开(公告)日：2003-07-15
申请号：US10150385
申请日：2002-05-17
申请人： Teng-Chun Tsai , Chia-Lin Hsu , Yi-Fang Cheng , Yi-Hsiung Lin
发明人： Teng-Chun Tsai , Chia-Lin Hsu , Yi-Fang Cheng , Yi-Hsiung Lin
IPC分类号： H01L218242
CPC分类号： H01L27/108 , H01L28/90
摘要： A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.
摘要翻译：公开了一种用于制造垂直三维金属 - 绝缘体 - 金属电容器（MIM电容器）结构的方法。本发明在衬底上利用垂直三维MIM电容器结构，以降低逻辑集成电路中MIM电容器的结构面积，并在芯片上的相同电容下对铜双镶嵌工艺进行集成; 因此，可以增加垂直三维电容器的电容密度。此外，本发明提供一种制造与铜双镶嵌结构的制造兼容的垂直三维MIM电容器结构的方法，使得可以减少在制造过程中的光掩模的数量。

3. 发明授权

US07199059B2 Method for removing polymer as etching residue 有权
标题翻译：去除聚合物作为蚀刻残留物的方法
公开(公告)号：US07199059B2
公开(公告)日：2007-04-03
申请号：US10904149
申请日：2004-10-26
申请人： Yi-Fang Cheng , Shan-Jen Yu , Cheng-Kweng Chen , Yu-Ming Huang
发明人： Yi-Fang Cheng , Shan-Jen Yu , Cheng-Kweng Chen , Yu-Ming Huang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/02063 , H01L21/76813 , H01L21/76814 , H01L21/76829 , Y10S438/945
摘要： A method for removing polymer as an etching residue is described. A substrate with polymer as an etching residue thereon is provided, and a hydrogen-containing plasma is used to treat the substrate. A wet clean step is then performed to remove the polymer from the substrate. The treatment using hydrogen-containing plasma can change the chemical property of the polymer, so that the polymer can be removed more easily in the subsequent wet clean step.
摘要翻译：描述了除去作为蚀刻残渣的聚合物的方法。提供了具有聚合物作为蚀刻残留物的基板，并且使用含氢等离子体来处理基板。然后进行湿式清洁步骤以从基材中除去聚合物。使用含氢等离子体的处理可以改变聚合物的化学性质，使得在随后的湿清洁步骤中可以更容易地除去聚合物。

4. 发明申请

US20060138925A1 PLASMA PROCESSING DEVICE HAVING A RING-SHAPED AIR CHAMBER FOR HEAT DISSIPATION 审中-公开
标题翻译：具有环形空气室的等离子体处理装置用于散热
公开(公告)号：US20060138925A1
公开(公告)日：2006-06-29
申请号：US10905333
申请日：2004-12-28
申请人： Yi-Fang Cheng , Hsiao-Pang Chou
发明人： Yi-Fang Cheng , Hsiao-Pang Chou
IPC分类号： H01J7/24 , H01J17/26
CPC分类号： H01J37/32449 , H01J37/3244 , H01J37/32724
摘要： A plasma processing device has a housing, a metal plate, an inner ring, and an outer ring. A vacuum chamber is formed in the housing. An air vent is installed on an upper end of the vacuum chamber for venting gaseous reactants into the vacuum chamber when performing a plasma process. The metal plate has a channel for venting gaseous matter and at least a vertical vent hole for guiding the gaseous reactants into the vacuum chamber. The inner ring and the outer ring are positioned between the housing and the metal plate, and the inner ring is surrounded by the outer ring. An air chamber formed between the inner ring and the outer ring connects with the channel of the metal plate.
摘要翻译：等离子体处理装置具有外壳，金属板，内圈和外圈。在壳体中形成真空室。在真空室的上端安装有排气孔，用于在进行等离子体处理时将气体反应物排放到真空室中。金属板具有用于排出气态物质的通道和至少一个垂直通风孔，用于将气态反应物引导到真空室中。内圈和外圈位于外壳和金属板之间，内圈由外圈包围。形成在内圈和外圈之间的空气室与金属板的通道连接。

5. 发明申请

US20080311743A1 METHOD OF FABRICATING OPENING AND PLUG 审中-公开
标题翻译：打开和插拔的方法
公开(公告)号：US20080311743A1
公开(公告)日：2008-12-18
申请号：US12190580
申请日：2008-08-12
申请人： Yi-Fang Cheng , Chopin Chou
发明人： Yi-Fang Cheng , Chopin Chou
IPC分类号： H01L21/768
CPC分类号： H01L21/31144 , H01L21/3105 , H01L21/76807 , H01L21/76813 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L2221/1063
摘要： A method of fabricating an opening or plug is provided. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer and prevent the later formed photoresist layer from reacting with the running-off composition component from the dielectric layer. Therefore, the problem of incomplete development due to outgasing of the dielectric layer can be solved. Additionally, in the procedure for forming a plug, before a block layer is forming on a surface of a via, a treatment process is performed to form a film on the surface of the via. Therefore, the problem of having defects inside the block layer caused by outgasing of the dielectric layer can be overcome.
摘要翻译：提供一种制造开口或插头的方法。在形成开口的过程中，在电介质层上形成光致抗蚀剂层之前，进行处理工艺以在电介质层上形成膜，其中该膜可以抑制电介质层的退磁现象并防止后来形成光致抗蚀剂层与来自电介质层的流逝组合物组分反应。因此，可以解决由于电介质层的消失而导致的不完全发展的问题。此外，在形成插塞的步骤中，在通孔的表面上形成阻挡层之前，进行处理工艺以在通孔的表面上形成膜。因此，可以克服由电介质层的延长引起的阻挡层内的缺陷的问题。

6. 发明申请

US20060089003A1 METHOD FOR REMOVING POLYMER AS ETCHING RESIDUE 有权
标题翻译：用于去除聚合物作为蚀刻残留物的方法
公开(公告)号：US20060089003A1
公开(公告)日：2006-04-27
申请号：US10904149
申请日：2004-10-26
申请人： Yi-Fang Cheng , Shan-Jen Yu , Cheng-Kweng Chen , Yu-Ming Huang
发明人： Yi-Fang Cheng , Shan-Jen Yu , Cheng-Kweng Chen , Yu-Ming Huang
IPC分类号： H01L21/44
CPC分类号： H01L21/02063 , H01L21/76813 , H01L21/76814 , H01L21/76829 , Y10S438/945
摘要： A method for removing polymer as an etching residue is described. A substrate with polymer as an etching residue thereon is provided, and a hydrogen-containing plasma is used to treat the substrate. A wet clean step is then performed to remove the polymer from the substrate. The treatment using hydrogen-containing plasma can change the chemical property of the polymer, so that the polymer can be removed more easily in the subsequent wet clean step.
摘要翻译：描述了除去作为蚀刻残渣的聚合物的方法。提供了具有聚合物作为蚀刻残留物的基板，并且使用含氢等离子体来处理基板。然后进行湿式清洁步骤以从基材中除去聚合物。使用含氢等离子体的处理可以改变聚合物的化学性质，使得在随后的湿清洁步骤中可以更容易地除去聚合物。

7. 发明授权

US07514365B2 Method of fabricating opening and plug 有权
标题翻译：制造开口和插头的方法
公开(公告)号：US07514365B2
公开(公告)日：2009-04-07
申请号：US11164273
申请日：2005-11-16
申请人： Yi-Fang Cheng , Chopin Chou
发明人： Yi-Fang Cheng , Chopin Chou
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/3105 , H01L21/76807 , H01L21/76813 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L2221/1063
摘要： A method of fabricating an opening or plug. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer and prevent the later formed photoresist layer from reacting with the running-off composition component from the dielectric layer. Therefore, the problem of incomplete development due to outgasing of the dielectric layer can be solved. Additionally, in the procedure for forming a plug, before a block layer is forming on a surface of a via, a treatment process is performed to form a film on the surface of the via. Therefore, the problem of having defects inside the block layer caused by outgasing of the dielectric layer can be overcome.
摘要翻译：一种制造开口或塞子的方法。在形成开口的过程中，在电介质层上形成光致抗蚀剂层之前，进行处理工艺以在电介质层上形成膜，其中该膜可以抑制电介质层的退磁现象并防止后来形成光致抗蚀剂层与来自电介质层的流逝组合物组分反应。因此，可以解决由于电介质层的消失而导致的不完全发展的问题。此外，在形成插塞的步骤中，在通孔的表面上形成阻挡层之前，进行处理工艺以在通孔的表面上形成膜。因此，可以克服由电介质层的延长引起的阻挡层内的缺陷的问题。

8. 发明申请

US20070111513A1 METHOD OF FABRICATING OPENING AND PLUG 有权
标题翻译：打开和插拔的方法
公开(公告)号：US20070111513A1
公开(公告)日：2007-05-17
申请号：US11164273
申请日：2005-11-16
申请人： Yi-Fang Cheng , Chopin Chou
发明人： Yi-Fang Cheng , Chopin Chou
IPC分类号： H01L21/4763 , H01L21/311 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/3105 , H01L21/76807 , H01L21/76813 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L2221/1063
摘要： A method of fabricating an opening or plug. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer and prevent the later formed photoresist layer from reacting with the running-off composition component from the dielectric layer. Therefore, the problem of incomplete development due to outgasing of the dielectric layer can be solved. Additionally, in the procedure for forming a plug, before a block layer is forming on a surface of a via, a treatment process is performed to form a film on the surface of the via. Therefore, the problem of having defects inside the block layer caused by outgasing of the dielectric layer can be overcome.
摘要翻译：一种制造开口或塞子的方法。在形成开口的过程中，在电介质层上形成光致抗蚀剂层之前，进行处理工艺以在电介质层上形成膜，其中该膜可以抑制电介质层的退磁现象并防止后来形成光致抗蚀剂层与来自电介质层的流逝组合物组分反应。因此，可以解决由于电介质层的消失而导致的不完全发展的问题。此外，在形成插塞的步骤中，在通孔的表面上形成阻挡层之前，进行处理工艺以在通孔的表面上形成膜。因此，可以克服由电介质层的延长引起的阻挡层内的缺陷的问题。

9. 发明授权

US06440861B1 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06440861B1
公开(公告)日：2002-08-27
申请号：US09652471
申请日：2000-08-31
申请人： Chih-Chien Liu , Jui-Tsen Huang , Yi-Fang Cheng , Ming-Sheng Yang
发明人： Chih-Chien Liu , Jui-Tsen Huang , Yi-Fang Cheng , Ming-Sheng Yang
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1063
摘要： A method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench. Finally, chemical-mechanical polishing is conducted to remove excess conductive material above the second dielectric layer.
摘要翻译：形成双镶嵌结构的方法。第一电介质层和第二电介质层依次形成在衬底上。在第二介电层上形成第一光致抗蚀剂层。进行光刻和蚀刻操作以去除第二介电层和第一介电层的一部分，从而形成通孔。保形第三电介质层涂覆在第二电介质层的表面和通孔开口的内表面上。保形第三电介质层形成衬里电介质层。在第二电介质层上形成第二光致抗蚀剂层，然后对第二光致抗蚀剂层进行图案化。使用图案化的第二光致抗蚀剂层作为掩模，去除第二介电层的一部分以形成沟槽。去除图案化的第二光致抗蚀剂层。导电材料沉积在衬底上以填充通孔和沟槽。最后，进行化学机械抛光以除去第二介电层上方的多余的导电材料。

10. 发明申请

US20050176237A1 In-situ liner formation during reactive ion etch 审中-公开
标题翻译：反应离子蚀刻期间的原位衬垫形成
公开(公告)号：US20050176237A1
公开(公告)日：2005-08-11
申请号：US10772777
申请日：2004-02-05
申请人： Theodorus Standaert , Bernd Kastenmeier , Yi-Hsiung Lin , Yi-Fang Cheng , Larry Clevenger , Stephen Greco , O Sung Kwon
发明人： Theodorus Standaert , Bernd Kastenmeier , Yi-Hsiung Lin , Yi-Fang Cheng , Larry Clevenger , Stephen Greco , O Sung Kwon
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76867
摘要： In damascene processing, metal hardmask sputtering redeposition that occurs during reactive ion etching (RIE) is exploited to produce, during the RIE process, a desired barrier metal liner on the etched feature.
摘要翻译：在镶嵌加工中，在反应离子蚀刻（RIE）期间发生的金属硬掩模溅射再沉积被利用以在RIE工艺期间在蚀刻特征上产生期望的阻挡金属衬垫。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式