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1. 发明授权

US07689941B1 Write margin calculation tool for dual-port random-access-memory circuitry 失效
标题翻译：用于双端口随机存取存储器电路的写裕量计算工具
公开(公告)号：US07689941B1
公开(公告)日：2010-03-30
申请号：US11803091
申请日：2007-05-11
申请人： Teng Chow Ooi , Yanzhong Xu , Jeffrey T. Watt , Haiming Yu
发明人： Teng Chow Ooi , Yanzhong Xu , Jeffrey T. Watt , Haiming Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.
摘要翻译：提供了用于计算双端口存储器的写入边距的系统和方法。使用电路设计工具生成双端口存储器阵列单元的设计。用户修改双端口存储器阵列单元的设计以并入两个电压源。电压源用于表示存储单元上的差分噪声。写余量计算工具使用电路仿真工具对修改后的双端口存储器阵列单元进行写入读取操作的瞬态仿真。在瞬态模拟期间，电压源上的电压电平有系统地变化。通过分析用于电压源的每个电压电平的瞬态模拟结果来确定双端口存储器的写入裕度。

2. 发明授权

US08120407B1 Techniques for varying phase shifts in periodic signals 有权
标题翻译：改变周期信号相移的技术
公开(公告)号：US08120407B1
公开(公告)日：2012-02-21
申请号：US12642738
申请日：2009-12-18
申请人： Teng Chow Ooi , Eng Huat Lee , Chuan Khye Chai , Yew Fatt (Edwin) Kok , Sergey Shumarayev
发明人： Teng Chow Ooi , Eng Huat Lee , Chuan Khye Chai , Yew Fatt (Edwin) Kok , Sergey Shumarayev
IPC分类号： H03K23/00
CPC分类号： H03K5/135 , H03K2005/00286
摘要： A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value.
摘要翻译：电路包括相位检测电路和相变电路。相位检测电路将第一周期性信号的相位与输入信号进行比较，以产生增益信号。当增益信号具有第一值时，相变电路在第一和第二方向上向第一周期性信号提供相移。响应于增益信号从第一值改变到第二值，相变电路增加提供给第一周期信号的第一方向的相移。当增益信号具有小于当增益信号具有第二值时在第一方向上提供给第一周期信号的相移的第二值时，相变电路在第二方向上向第一周期信号提供相移。

3. 发明授权

US08693616B1 IC and a method for flexible integer and fractional divisions 有权
$IC and a method for flexible integer and fractional divisions$
标题翻译： IC和一种灵活的整数和分数分割的方法
公开(公告)号：US08693616B1
公开(公告)日：2014-04-08
申请号：US13431905
申请日：2012-03-27
申请人： Chuan Thim Khoŕ , Teng Chow Ooi
发明人： Chuan Thim Khoŕ , Teng Chow Ooi
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K21/00 , G06F1/08 , H03K21/023 , H03K23/42 , H03K23/54 , H03L7/193 , H03L7/1974
摘要： An IC that performs integer and fractional divisions is disclosed. The IC comprises a plurality of shift registers that forms a shift register ring. Consecutive shift registers are coupled to each other through a multiplexer. The IC also includes a multiplexer controller that determines the shift registers to be activated within the shift register ring. The multiplexer controller determines the activation based upon a divisional factor. The IC also includes a pattern controller that generates the control signal to program the shift register.
摘要翻译：公开了一种执行整数和分数分割的IC。 IC包括形成移位寄存器环的多个移位寄存器。连续移位寄存器通过多路复用器彼此耦合。 IC还包括多路复用器控制器，其确定在移位寄存器环内被激活的移位寄存器。复用器控制器基于分割因子确定激活。 IC还包括产生控制信号以对移位寄存器进行编程的模式控制器。

4. 发明授权

US08687738B1 Circuits and methods using a majority vote 有权
标题翻译：使用多数票的电路和方法
公开(公告)号：US08687738B1
公开(公告)日：2014-04-01
申请号：US13078421
申请日：2011-04-01
申请人： Swee Wah Lee , Teng Chow Ooi , Chuan Khye Chai
发明人： Swee Wah Lee , Teng Chow Ooi , Chuan Khye Chai
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H04L7/0025
摘要： A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.
摘要翻译：时钟数据恢复电路包括相位检测器电路，多数选择电路和相移电路。相位检测器电路可操作以将周期信号的相位与数据信号的相位进行比较，以产生相位误差信号。多数选民电路包括移位寄存器电路。移位寄存器电路可操作以基于相位误差信号产生输出信号。多数选民电路可操作以基于移位寄存器电路的输出信号产生相位误差信号的多数票。相移电路可操作以基于由多数选举电路产生的多数投票来设置周期信号的相位。

5. 发明授权

US07760577B1 Programmable power down scheme for embedded memory block 有权
标题翻译：嵌入式内存块的可编程掉电方案
公开(公告)号：US07760577B1
公开(公告)日：2010-07-20
申请号：US12212768
申请日：2008-09-18
申请人： Wei Yee Koay , Teng Chow Ooi , Ngee Kiat Chieng , Yau Kok Lai , Mei Ching Lim
发明人： Wei Yee Koay , Teng Chow Ooi , Ngee Kiat Chieng , Yau Kok Lai , Mei Ching Lim
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/063 , G11C7/22 , G11C2207/2227
摘要： An integrated circuit configured to selectively provide power to used portions of a memory array is presented. The integrated circuit includes an array of memory cells for storing digital data and a power bus interconnecting structure. The power bus interconnecting structure includes global power buses in communication with local power buses through programmable vias. The array of memory cells are remapped so that unused column portions of the memory array become unused row portions of the memory array. The programmable vias are selectively located during design of the integrated circuit, providing power to the used portions of the memory array.
摘要翻译：提出了被配置为向存储器阵列的使用部分选择性地提供电力的集成电路。集成电路包括用于存储数字数据的存储单元阵列和电力总线互连结构。电源总线互连结构包括通过可编程通孔与本地电源总线通信的全局电源总线。存储器单元的阵列被重新映射，使得存储器阵列的未使用的列部分变成存储器阵列的未使用的行部分。在集成电路的设计期间，可选择性地定位可编程通孔，为存储器阵列的使用部分提供电力。

6. 发明授权

US08666013B1 Techniques for clock data recovery 有权
标题翻译：时钟数据恢复技术
公开(公告)号：US08666013B1
公开(公告)日：2014-03-04
申请号：US13053797
申请日：2011-03-22
申请人： Chuan Thim Khor , Teng Chow Ooi
发明人： Chuan Thim Khor , Teng Chow Ooi
IPC分类号： H04L7/033 , H03L7/06
CPC分类号： H04L7/02 , H03L7/07 , H03L7/0816 , H04L7/0025 , H04L7/033
摘要： A clock data recovery circuit includes a phase detector circuit, a filter circuit, a parts per million (PPM) detector circuit, a PPM decoder circuit, a summation circuit, and a phase interpolator circuit. The phase detector circuit generates a phase error signal based on a periodic signal and a data signal. The filter circuit generates a filtered signal based on the phase error signal. The PPM detector circuit and the PPM decoder circuit generate control signals based on the filtered signal. The phase interpolator circuit generates the periodic signal. The clock data recovery circuit adjusts a phase of the periodic signal based on the filtered signal and the control signals in response to variations in a data rate of the data signal using spread-spectrum clocking in order to track changes in the data rate of the data signal.
摘要翻译：时钟数据恢复电路包括相位检测器电路，滤波器电路，百万分之一（PPM）检测器电路，PPM解码器电路，求和电路和相位内插器电路。相位检测器电路基于周期信号和数据信号产生相位误差信号。滤波电路根据相位误差信号产生滤波信号。 PPM检测器电路和PPM解码器电路基于滤波信号产生控制信号。相位内插器电路产生周期信号。时钟数据恢复电路根据经滤波的信号和控制信号调整周期信号的相位，以响应数据信号的数据速率的变化，使用扩频时钟来跟踪数据的数据速率的变化信号。

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