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1. 发明授权

US06710427B2 Distributed power device with dual function minority carrier reduction 有权
标题翻译：具有双功能少数载波减少的分布式功率器件
公开(公告)号：US06710427B2
公开(公告)日：2004-03-23
申请号：US10167136
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
IPC分类号： H01L2900
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D4) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region (56) reducing the minority carrier lifetime to provide increased switching speed of the large power FET.
摘要翻译：一种分布式功率器件（100），包括通过深n型区域（16）彼此分离的多个槽区（90），并且在每个槽区中形成有多个晶体管（50）。每个槽区中的多个晶体管（50）与其它罐区中的晶体管相互连接以形成大功率FET，由此深n型区域将罐区彼此隔离。第一寄生二极管（D5）从每个槽区限定到埋层，并且在掩埋层和衬底之间限定第二寄生二极管（D4）。深n型区域相对于多个罐区域分布第一和第二寄生二极管，优选地由P-epi罐组成。深n型区域还分布形成在罐区域下方的NBL层（14）的电阻。分布式寄生二极管和NBL层的电阻有利地提供NBL层和衬底之间的寄生二极管（D4）将永远不会被正向偏置。此外，每个槽区具有重掺杂的p型区（56），减少了少量载流子寿命，以提供大功率FET的提高的开关速度。

2. 发明授权

US06784493B2 Line self protecting multiple output power IC architecture 有权
标题翻译：线路自保护多输出电源IC架构
公开(公告)号：US06784493B2
公开(公告)日：2004-08-31
申请号：US10166956
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
IPC分类号： H01L2900
CPC分类号： H01L29/7835 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/1083
摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
摘要翻译：一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

3. 发明授权

US06709900B2 Method of fabricating integrated system on a chip protection circuit 有权
标题翻译：在芯片保护电路上制造集成系统的方法
公开(公告)号：US06709900B2
公开(公告)日：2004-03-23
申请号：US10166964
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
IPC分类号： H01L21332
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
摘要翻译：一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

4. 发明授权

US06770935B2 Array of transistors with low voltage collector protection 有权
标题翻译：具有低电压采集器保护的晶体管阵列
公开(公告)号：US06770935B2
公开(公告)日：2004-08-03
申请号：US10166965
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , Dale Skelton
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , Dale Skelton
IPC分类号： H01L2701
CPC分类号： H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer. The guardring is preferably grounded when utilized as the low side transistor to collect minority carriers.
摘要翻译：形成在p型层（34）中的晶体管（50）的阵列（90），并且包括在每个晶体管的漏极附近横向延伸以收集晶体管的少数载流子的第二重掺杂p型区域（56）。在p型层（34）中形成深n型区域（16）并邻近n型掩埋层（14），形成围绕多个晶体管的漏极区域的保护。晶体管阵列可以并联连接以形成大功率FET，由此重掺杂的第二p型区域（56）减少了靠近晶体管漏极的少数载流子寿命。防护（14,16）收集少数载流子（T1），并与晶体管的漏极隔离。优选地，晶体管形成在由护罩隔离的P-epi罐中。 P-epi罐优选地形成在掩埋NBL层上，并且深n型区域是延伸到掩埋NBL层的N +阱。当用作低侧晶体管以收集少数载流子时，护罩优选地接地。

5. 发明授权

US06661216B1 Apparatus and method for controlling startup of a precharged switching regulator 有权
标题翻译：用于控制预充电开关调节器启动的装置和方法
公开(公告)号：US06661216B1
公开(公告)日：2003-12-09
申请号：US10227942
申请日：2002-08-26
申请人： David A. Grant , David D. Briggs , Ayesha I. Mayhugh
发明人： David A. Grant , David D. Briggs , Ayesha I. Mayhugh
IPC分类号： G05F158
CPC分类号： H02M1/36 , Y10S323/901
摘要： An apparatus for presenting a regulated output at an output locus established at a precharge level includes: (a) an error indicator generating an error signal indicating difference between a reference signal and a sensed signal; (b) a pulse indicator coupled with the error indicator generating a pulse signal indicating difference between the error signal and a periodic signal; (c) a switching device responding to the pulse signal effecting coupling of the output locus with a first terminal or a second terminal depending upon whether the pulse signal is at a first level or a second level; and (d) a driver controller coupled with the pulse indicator and the switching device that provides a control signal to the switching device indicating at least one characteristic of the pulse signal. The switching device is operative or inoperative depending upon whether the control signal is in a first state or a second state.
摘要翻译：在预充电电平处建立的输出轨迹处呈现稳压输出的装置包括：（a）产生指示参考信号和感测信号之间差异的误差信号的误差指示器; （b）与误差指示器耦合的脉冲指示器，产生指示误差信号和周期信号之间的差异的脉冲信号; （c）根据所述脉冲信号是处于第一电平还是第二电平，响应于所述脉冲信号响应所述输出轨迹与第一端子或第二端子的耦合的开关装置; 以及（d）与所述脉冲指示器和所述开关装置耦合的驱动器控制器，其向所述开关装置提供指示所述脉冲信号的至少一个特性的控制信号。根据控制信号是处于第一状态还是第二状态，开关装置可操作或不起作用。

6. 发明授权

US06727752B2 Modulation scheme for switching amplifiers to reduce filtering requirements and crossover distortion 有权
标题翻译：用于开关放大器的调制方案，以减少滤波要求和交叉失真
公开(公告)号：US06727752B2
公开(公告)日：2004-04-27
申请号：US10156926
申请日：2002-05-29
申请人： David L. Skinner , Wayne Tien-Feng Chen , David A. Grant , Vadim Ivanov
发明人： David L. Skinner , Wayne Tien-Feng Chen , David A. Grant , Vadim Ivanov
IPC分类号： H03F3217
CPC分类号： H03F3/2173 , H02M1/083 , H02M1/44 , H02M3/158 , H02M2001/0045 , H02M2003/1555
摘要： A modulation scheme can drive an associated load that is coupled between a pair of outputs by providing a switching signal at one of the outputs and a non-switching signal at the other output independent of the direction of current relative to the respective outputs. Because switching occurs only at one of the outputs in this mode of operation, a single filter can be used to mitigate switching noise at the switching output. Another aspect relates to another mode of operation in which one or both of the outputs can be controlled to operate linearly, such as during a zero crossing condition, so as to help reduce crossover distortion.
摘要翻译：调制方案可以通过在输出之一处提供切换信号和在另一输出处提供非切换信号来驱动耦合在一对输出之间的相关联的负载，而不依赖于相对于各个输出的电流方向。因为在这种工作模式下，仅在其中一个输出进行切换，所以可以使用单个滤波器来减轻开关输出端的开关噪声。另一方面涉及另一种操作模式，其中一个或两个输出可被控制为线性运行，例如在零交叉状态期间，以帮助减少交叉失真。

7. 发明授权

US06812782B2 Switch mode converter that allows 100% duty cycle on gate driver 有权
标题翻译：开关模式转换器允许栅极驱动器上的100％占空比
公开(公告)号：US06812782B2
公开(公告)日：2004-11-02
申请号：US10280743
申请日：2002-10-25
申请人： David A. Grant
发明人： David A. Grant
IPC分类号： G06F140
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A switch mode converter uses the bootstrap capacitor 30 to operate all the way to 100% duty cycle by adding only a very small amount of low-area extra circuitry. The additional circuitry includes a charge pump 40 and a duty cycle detect device 42. When the duty cycle detect device 42 detects that the converter is attempting to operate in 100% duty cycle, the charge pump 40 provides additional charge to the bootstrap capacitor 30 to ensure that the 100% duty cycle is maintained.
摘要翻译：开关模式转换器使用自举电容器30通过仅添加非常少量的低区域额外电路而一直操作到100％占空比。附加电路包括电荷泵40和占空比检测装置42.当占空比检测装置42检测到转换器试图以100％占空比工作时，电荷泵40向自举电容器30提供额外的电荷，确保保持100％的占空比。

8. 发明授权

US06744243B2 System and method for dynamically regulating a step down power supply 有权
标题翻译：动态调节降压电源的系统和方法
公开(公告)号：US06744243B2
公开(公告)日：2004-06-01
申请号：US09895959
申请日：2001-06-28
申请人： David G. Daniels , Dale J. Skelton , Ayesha I. Mayhugh , David A. Grant
发明人： David G. Daniels , Dale J. Skelton , Ayesha I. Mayhugh , David A. Grant
IPC分类号： G05F144
CPC分类号： G05F1/40 , G06F1/26
摘要： A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the integrated circuit. The step down power supply is operable to receive an input voltage and to generate an output voltage based on the input voltage. The feedback compensation circuit includes a line regulation circuit. The line regulation circuit is operable to receive the input voltage and a reference voltage. The line regulation circuit is also operable to generate an offset voltage based on the input voltage and the reference voltage.
摘要翻译：在集成电路上提供低增益反馈补偿电路。反馈补偿电路耦合到集成电路上的降压电源。降压电源可操作以接收输入电压并且基于输入电压产生输出电压。反馈补偿电路包括线路调节电路。线路调节电路可操作以接收输入电压和参考电压。线路调节电路还可操作以基于输入电压和参考电压产生偏移电压。

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