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1. 发明授权

US08461895B2 Per die temperature programming for thermally efficient integrated circuit (IC) operation 有权
标题翻译：用于热效率集成电路（IC）操作的每芯片温度编程
公开(公告)号：US08461895B2
公开(公告)日：2013-06-11
申请号：US13281319
申请日：2011-10-25
申请人： Tawfik Arabi , Ali Muhtaroglu
发明人： Tawfik Arabi , Ali Muhtaroglu
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/3867 , G06F9/3885 , Y02D10/16
摘要： Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.
摘要翻译：描述了为热效率集成电路（IC）操作提供每个管芯温度编程的方法和装置。在一些实施例中，确定IC部件的结温，例如以降低功耗和/或改善性能。还描述了其它实施例。

2. 发明授权

US06747470B2 Method and apparatus for on-die voltage fluctuation detection 有权
公开(公告)号：US06747470B2
公开(公告)日：2004-06-08
申请号：US10021055
申请日：2001-12-19
申请人： Ali Muhtaroglu , Kent Callahan , Tawfik Arabi , Greg F. Taylor
发明人： Ali Muhtaroglu , Kent Callahan , Tawfik Arabi , Greg F. Taylor
IPC分类号： G01R3102
CPC分类号： G01R19/16552 , G01R19/16519 , G01R19/16566 , G01R31/275
摘要： An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die. The second detector unit may provide (or output) a second signal indicative of a voltage fluctuation (or voltage droop) of the second voltage signals.

3. 发明授权

US07685445B2 Per die voltage programming for energy efficient integrated circuit (IC) operation 失效
标题翻译：用于节能集成电路（IC）操作的每芯片电压编程
公开(公告)号：US07685445B2
公开(公告)日：2010-03-23
申请号：US11478475
申请日：2006-06-29
申请人： Tawfik Arabi , Ali Muhtaroglu , Michael Bitan
发明人： Tawfik Arabi , Ali Muhtaroglu , Michael Bitan
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Methods and apparatus to provide per die voltage programming for energy efficient integrated circuit (IC) operation are described. In some embodiments, the voltage potential supplied to an IC component is lowered below a peak performance voltage level, e.g., to reduce power consumption by the component. Other embodiments are also described.
摘要翻译：描述了提供用于节能集成电路（IC）操作的每个芯片电压编程的方法和装置。在一些实施例中，提供给IC部件的电压电位降低到峰值性能电压电平以下，例如降低部件的功耗。还描述了其它实施例。

4. 发明申请

US20080001795A1 Per die voltage programming for energy efficient integrated circuit (IC) operation 失效
标题翻译：用于节能集成电路（IC）操作的每芯片电压编程
公开(公告)号：US20080001795A1
公开(公告)日：2008-01-03
申请号：US11478475
申请日：2006-06-29
申请人： Tawfik Arabi , Ali Muhtaroglu , Michael Bitan
发明人： Tawfik Arabi , Ali Muhtaroglu , Michael Bitan
IPC分类号： H03M7/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Methods and apparatus to provide per die voltage programming for energy efficient integrated circuit (IC) operation are described. In some embodiments, the voltage potential supplied to an IC component is lowered below a peak performance voltage level, e.g., to reduce power consumption by the component. Other embodiments are also described.
摘要翻译：描述了提供用于节能集成电路（IC）操作的每个芯片电压编程的方法和装置。在一些实施例中，提供给IC部件的电压电位降低到峰值性能电压电平以下，例如降低部件的功耗。还描述了其它实施例。

5. 发明申请

US20080001634A1 Per die temperature programming for thermally efficient integrated circuit (IC) operation 有权
标题翻译：用于热效率集成电路（IC）操作的每芯片温度编程
公开(公告)号：US20080001634A1
公开(公告)日：2008-01-03
申请号：US11478472
申请日：2006-06-29
申请人： Tawfik Arabi , Ali Muhtaroglu
发明人： Tawfik Arabi , Ali Muhtaroglu
IPC分类号： H03K19/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/3867 , G06F9/3885 , Y02D10/16
摘要： Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.
摘要翻译：描述了为热效率集成电路（IC）操作提供每个管芯温度编程的方法和装置。在一些实施例中，确定IC部件的结温，例如以降低功耗和/或改善性能。还描述了其它实施例。

6. 发明申请

US20120133578A1 PER DIE TEMPERATURE PROGRAMMING FOR THERMALLY EFFICIENT INTEGRATED CIRCUIT (IC) OPERATION 有权
标题翻译：用于热效率集成电路（IC）操作的每个温度编程
公开(公告)号：US20120133578A1
公开(公告)日：2012-05-31
申请号：US13281319
申请日：2011-10-25
申请人： Tawfik Arabi , Ali Muhtaroglu
发明人： Tawfik Arabi , Ali Muhtaroglu
IPC分类号： G09G3/36 , G11C8/18
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/3867 , G06F9/3885 , Y02D10/16
摘要： Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.
摘要翻译：描述了为热效率集成电路（IC）操作提供每个管芯温度编程的方法和装置。在一些实施例中，确定IC部件的结温，例如以降低功耗和/或改善性能。还描述了其它实施例。

7. 发明授权

US08044697B2 Per die temperature programming for thermally efficient integrated circuit (IC) operation 有权
标题翻译：用于热效率集成电路（IC）操作的每芯片温度编程
公开(公告)号：US08044697B2
公开(公告)日：2011-10-25
申请号：US11478472
申请日：2006-06-29
申请人： Tawfik Arabi , Ali Muhtaroglu
发明人： Tawfik Arabi , Ali Muhtaroglu
IPC分类号： H03K3/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F9/3867 , G06F9/3885 , Y02D10/16
摘要： Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e.g., to reduce power consumption and/or improve performance. Other embodiments are also described.
摘要翻译：描述了为热效率集成电路（IC）操作提供每个管芯温度编程的方法和装置。在一些实施例中，确定IC部件的结温，例如以降低功耗和/或改善性能。还描述了其它实施例。

8. 发明授权

US07157924B2 Method and apparatus for on-die voltage fluctuation detection 有权
标题翻译：用于片上电压波动检测的方法和装置
公开(公告)号：US07157924B2
公开(公告)日：2007-01-02
申请号：US10683189
申请日：2003-10-10
申请人： Ali Muhtaroglu , Kent Callahan , Tawfik Arabi , Greg F. Taylor
发明人： Ali Muhtaroglu , Kent Callahan , Tawfik Arabi , Greg F. Taylor
IPC分类号： G01R31/26
CPC分类号： G01R19/16552 , G01R19/16519 , G01R19/16566 , G01R31/275
摘要： An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die. The second detector unit may provide (or output) a second signal indicative of a voltage fluctuation (or voltage droop) of the second voltage signals.
摘要翻译：提供了一种片上设备来测量/检测电压波动。这可以包括用于产生差分参考信号（例如差分电流信号）的控制单元，第一检测器单元和第二检测器单元。可以基于Vcc参考信号和Vss参考信号来生成差分参考信号。第一检测器单元可以从控制单元接收差分参考信号，并且可以从位于管芯上的第一被测器件（DUT）或从管芯上的第一区域接收第一电压信号（也称为监视信号）。第一检测器单元可以提供（或输出）指示第一电压信号的电压波动（电压下降或过冲）的第一信号。第二检测器单元可以从控制单元接收差分参考信号，并且可以从位于管芯上的被测试的第二被测器件（DUT）接收第二电压信号（也称为监视信号）。第二检测器单元可以提供（或输出）指示第二电压信号的电压波动（或电压下降）的第二信号。

9. 发明授权

US07228515B2 Methods and apparatuses for validating AC I/O loopback tests using delay modeling in RTL simulation 失效
标题翻译：在RTL仿真中使用延迟建模验证AC I / O环回测试的方法和设备
公开(公告)号：US07228515B2
公开(公告)日：2007-06-05
申请号：US10846721
申请日：2004-05-13
申请人： Bruce Querbach , Amjad Khan , Mike Tripp , Luis Briceno Guerrero , Marco A. Vindas Vargas , Ali Muhtaroglu
发明人： Bruce Querbach , Amjad Khan , Mike Tripp , Luis Briceno Guerrero , Marco A. Vindas Vargas , Ali Muhtaroglu
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031
摘要： Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.
摘要翻译：本发明的实施例提供了一种具有其中实现的可控延迟模型的逻辑仿真，其可用于通过引入允许逻辑模拟器来模拟模拟行为的延迟模型来验证硅前置环境中的AC I / O环回设计。对于本发明的一个实施例，选择固定的处理器比率，硬件描述语言的延迟语句对应于特定的时间延迟。这些固定值提供了准确确定和调整模拟仿真延迟的能力。

10. 发明授权

US07036061B2 Structural input levels testing using on-die levels generators 失效
公开(公告)号：US07036061B2
公开(公告)日：2006-04-25
申请号：US09941484
申请日：2001-08-28
申请人： Ali Muhtaroglu
发明人： Ali Muhtaroglu
IPC分类号： G01R31/28
CPC分类号： G01R31/31716 , G01R31/3004 , G01R31/3167 , G01R31/318572
摘要： A set of levels generating circuits, such as a set of digital-to-analog converters, is designed into an integrated circuit on-die. The levels generating circuits apply direct current (DC) voltage levels to on-die sense amplifiers to test sense amplifier trip points for “input low voltage” (VIL) and “input high voltage” (VIH). The levels generating circuits are controlled by a set of configuration bits, which may be accessible through the boundary-scan register or the input/output (I/O) loop back pattern generator. The levels generating circuitry allows testing of one number of integrated circuit input pins using a smaller number of input pins.

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