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1. 发明申请

US20080217786A1 Semiconductor device and method of manufacturing semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080217786A1
公开(公告)日：2008-09-11
申请号：US12010793
申请日：2008-01-30
申请人： Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
发明人： Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： G03F1/32 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05093 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48453 , H01L2224/48463 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/3025 , Y10S438/926 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps.A step of preparing a phase shift mask and a normal photomask.A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring.A step of stacking an interlayer insulating film on the second wiring layer.A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask.A step of burying a metal in the first opening and the second opening.A step of providing a pad to be overlaid on the first and second openings.
摘要翻译：根据本发明的一个实施例，制造半导体器件的方法包括以下步骤。制备相移掩模和普通光掩模的步骤。在半导体衬底上堆叠第一布线层，并且在第一布线层上进一步层叠第二布线层的步骤。第二布线层包括第二布线和第三布线。在第二布线层上堆叠层间绝缘膜的步骤。在层间绝缘膜中形成第二布线露出的第一开口和通过光刻法使用普通光掩模使第三布线曝光的第二开口的步骤。在第一开口和第二开口中埋入金属的步骤。提供覆盖在第一和第二开口上的垫的步骤。

2. 发明授权

US07696081B2 Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns 失效
标题翻译：制造半导体器件的方法，其使用普通光掩模和相移掩模来定义互连图案
公开(公告)号：US07696081B2
公开(公告)日：2010-04-13
申请号：US12010793
申请日：2008-01-30
申请人： Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
发明人： Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
IPC分类号： H01L21/475
CPC分类号： G03F1/32 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05093 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48453 , H01L2224/48463 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/3025 , Y10S438/926 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps.A step of preparing a phase shift mask and a normal photomask.A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring.A step of stacking an interlayer insulating film on the second wiring layer.A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask.A step of burying a metal in the first opening and the second opening.A step of providing a pad to be overlaid on the first and second openings.
摘要翻译：根据本发明的一个实施例，制造半导体器件的方法包括以下步骤。制备相移掩模和普通光掩模的步骤。在半导体衬底上堆叠第一布线层，并且在第一布线层上进一步层叠第二布线层的步骤。第二布线层包括第二布线和第三布线。在第二布线层上堆叠层间绝缘膜的步骤。在层间绝缘膜中形成第二布线露出的第一开口和通过光刻法使用普通光掩模使第三布线曝光的第二开口的步骤。在第一开口和第二开口中埋入金属的步骤。提供覆盖在第一和第二开口上的垫的步骤。

3. 发明授权

US08084279B2 Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns 有权
标题翻译：制造半导体器件的方法，其使用普通光掩模和相移掩模来定义互连图案
公开(公告)号：US08084279B2
公开(公告)日：2011-12-27
申请号：US12720248
申请日：2010-03-09
申请人： Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
发明人： Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
IPC分类号： H01L21/66
CPC分类号： G03F1/32 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05093 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48453 , H01L2224/48463 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/3025 , Y10S438/926 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The second wiring layer includes a second wiring and third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.
摘要翻译：根据本发明的一个实施例，制造半导体器件的方法包括以下步骤。制备相移掩模和普通光掩模的步骤。在半导体衬底上堆叠第一布线层，并且在第一布线层上进一步层叠第二布线层的步骤。第二布线层包括第二布线和第三布线。在第二布线层上堆叠层间绝缘膜的步骤。在层间绝缘膜中形成第二布线露出的第一开口和通过光刻法使用普通光掩模使第三布线曝光的第二开口的步骤。在第一开口和第二开口中埋入金属的步骤。提供覆盖在第一和第二开口上的垫的步骤。

4. 发明申请

US20100159690A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE THAT USES BOTH A NORMAL PHOTOMASK AND A PHASE SHIFT MASK FOR DEFINING INTERCONNECT PATTERNS 有权
标题翻译：制造用于定义互连图案的正常光子晶体管和相移片掩模的半导体器件的制造方法
公开(公告)号：US20100159690A1
公开(公告)日：2010-06-24
申请号：US12720248
申请日：2010-03-09
申请人： Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
发明人： Tatsuo Kasaoka , Kiyohiko Sakakibara , Noboru Mori , Kazunobu Miki
IPC分类号： H01L21/768
CPC分类号： G03F1/32 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05093 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48453 , H01L2224/48463 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/3025 , Y10S438/926 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps.A step of preparing a phase shift mask and a normal photomask.A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The a second wiring layer includes a second wiring and a third wiring.A step of stacking an interlayer insulating film on the second wiring layer.A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask.A step of burying a metal in the first opening and the second opening.A step of providing a pad to be overlaid on the first and second openings.
摘要翻译：根据本发明的一个实施例，制造半导体器件的方法包括以下步骤。制备相移掩模和普通光掩模的步骤。在半导体衬底上堆叠第一布线层，并且在第一布线层上进一步层叠第二布线层的步骤。第二布线层包括第二布线和第三布线。在第二布线层上堆叠层间绝缘膜的步骤。在层间绝缘膜中形成第二布线露出的第一开口和通过光刻法使用普通光掩模使第三布线曝光的第二开口的步骤。在第一开口和第二开口中埋入金属的步骤。提供覆盖在第一和第二开口上的垫的步骤。

5. 发明申请

US20060163615A1 Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner 有权
标题翻译：具有集中布置缓冲器或保护电路的布局的半导体集成电路
公开(公告)号：US20060163615A1
公开(公告)日：2006-07-27
申请号：US11328194
申请日：2006-01-10
申请人： Tadashi Nakamura , Kiyohiko Sakakibara , Yutaka Takikawa
发明人： Tadashi Nakamura , Kiyohiko Sakakibara , Yutaka Takikawa
IPC分类号： H01L27/10
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11898
摘要： Buffers are arranged in a concentrated manner in a region distant from pads. The region refers to a region in a main region of a semiconductor integrated circuit, except for a central processing unit, a non-volatile memory and a volatile memory. As the buffer requiring a large area is not provided around the pad, a pitch between the pads or a pitch between the pad and an internal circuit (such as the central processing unit) can be made smaller and hence a chip size can be reduced. Therefore, a semiconductor integrated circuit capable of achieving a reduced chip size can be provided.
摘要翻译：缓冲器以集中的方式排列在远离焊盘的区域中。该区域是指除了中央处理单元，非易失性存储器和易失性存储器之外的半导体集成电路的主要区域中的区域。由于在焊盘周围不设置需要大面积的缓冲器，因此可以使焊盘之间的间距或焊盘与内部电路（例如中央处理单元）之间的间距更小，从而可以减小芯片尺寸。因此，能够提供能够实现芯片尺寸减小的半导体集成电路。

6. 发明授权

US06445617B1 Non-volatile semiconductor memory and methods of driving, operating, and manufacturing this memory 有权
公开(公告)号：US06445617B1
公开(公告)日：2002-09-03
申请号：US09505671
申请日：2000-02-17
申请人： Kiyohiko Sakakibara
发明人： Kiyohiko Sakakibara
IPC分类号： G11C1604
CPC分类号： H01L29/7885 , G11C16/0416 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3436 , H01L21/28273 , H01L29/66825
摘要： In a transistor including first and second diffused layers of a second conductance, opposite to each other through a channel region of a first conductance type, and a two-storied gate electrode on the channel region of the first conductance type, a channel region and one of the diffused layers are set at a first voltage level; the other thereof is set at a second voltage level; a control gate is set at the first or a third voltage level; a difference between the first and second voltage levels is set larger in absolute value than that between the first and third voltage levels; and a part of charges flowing in the channel region with respect to the transistor flowing a channel current is injected into the floating gate. This solves difficulties of large driving currents at write back, a long write back time, deterioration of channel conductance, and the like.

7. 发明授权

US5302543A Method of making a charge coupled device 失效
标题翻译：制造电荷耦合器件的方法
公开(公告)号：US5302543A
公开(公告)日：1994-04-12
申请号：US981846
申请日：1992-11-25
申请人： Kiyohiko Sakakibara
发明人： Kiyohiko Sakakibara
IPC分类号： H01L29/10 , H01L21/76
CPC分类号： H01L29/1062 , Y10S438/965
摘要： A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels. Therefore, the charges in the first horizontal channel can be transferred to the transfer channel by a gate voltage pinning the horizontal channel and the charges can be transferred from the first horizontal channel to the second horizontal channel by clock signals.
摘要翻译：电荷耦合器件包括第一导电类型半导体衬底中的第二导电类型的第一水平沟道，以及距离第一水平沟道预定距离的衬底中的第二导电类型的第二水平沟道;以及第二导电类型传输沟道，水平通道与第二水平通道，以使电荷能够从第一水平通道转移到第二水平通道。传输通道的钉扎电位的绝对值大于第一和第二水平通道的钉扎电位，并且固定传输沟道的栅极电压的绝对值小于固定第一和第二水平通道的栅极电压。因此，第一水平通道中的电荷可以通过锁定水平通道的栅极电压传送到传输通道，并且可以通过时钟信号将电荷从第一水平通道传送到第二水平通道。

8. 发明申请

US20050058551A1 Swash plate type variable displacement compressor 审中-公开
标题翻译：斜盘式可变排量压缩机
公开(公告)号：US20050058551A1
公开(公告)日：2005-03-17
申请号：US10933553
申请日：2004-09-03
申请人： Tomohiro Wakita , Osamu Nakayama , Kiyohiko Sakakibara , Hiroaki Kayukawa , Tetsuhiko Fukanuma , Yoshio Taneda , Tsuyoshi Yamaguchi
发明人： Tomohiro Wakita , Osamu Nakayama , Kiyohiko Sakakibara , Hiroaki Kayukawa , Tetsuhiko Fukanuma , Yoshio Taneda , Tsuyoshi Yamaguchi
IPC分类号： F04B27/08 , F04B1/14 , F04B27/10 , F04B27/18 , F04B1/26 , F04B1/12
CPC分类号： F04B27/1804 , F04B27/1054
摘要： A variable displacement compressor includes a swash plate guiding member that rotates integrally with and inclines relative to a drive shaft, a swash plate supported by the guiding member, and a piston engaged with the swash plate via a shoe. A clutch is located between the guiding member and the swash plate. The clutch is switched between an engaged state, where the clutch permits the guiding member and the swash plate to rotate integrally, and a disengaged state, where the clutch permits the guiding member and the swash plate to rotate relative to each other. Therefore, the compressor is capable of switching between a state where improving the displacement controllability is prioritized and a state where reduction of mechanical loss between the swash plate and the shoes is prioritized.
摘要翻译：可变排量压缩机包括相对于驱动轴一体地旋转并且相对于驱动轴倾斜的斜盘引导构件，由引导构件支撑的斜盘，以及经由鞋与斜盘接合的活塞。离合器位于引导构件和斜盘之间。离合器在接合状态之间切换，其中离合器允许引导构件和斜盘一体地旋转，并且离合器允许引导构件和斜盘相对于彼此旋转的分离状态。因此，压缩机能够在提高排量控制性优先的状态与斜盘和鞋之间的机械损失降低优先的状态之间进行切换。

9. 发明授权

US06566678B1 Semiconductor device having a solid-state image sensor 有权
标题翻译：具有固态图像传感器的半导体器件
公开(公告)号：US06566678B1
公开(公告)日：2003-05-20
申请号：US10121699
申请日：2002-04-15
申请人： Atsushi Maeda , Kiyohiko Sakakibara
发明人： Atsushi Maeda , Kiyohiko Sakakibara
IPC分类号： H01L2906
CPC分类号： H01L27/14601 , H01L27/14603 , H01L27/1463
摘要： A semiconductor device having a solid-state image sensor is provided in which the leakage current is less likely to occur. The surface portion of a P-type semiconductor substrate (1) is susceptible to various defects, which are likely to cause the leakage current. Accordingly an N-type buried channel layer (7a) is provided. While the potential is high in the vicinity of the surface of the P-type semiconductor substrate (1) where defects are present, the potential is minimized in the vicinity of the PN junction plane formed by the N-type buried channel layer (7a) and the P-type semiconductor substrate (1). Accordingly, when a transfer switch (M1) is operated, a channel is formed in the vicinity of this PN junction plane, so that a charge stored in an N-type source region (4a) of the photodiode (PD) can be transferred to an N-type drain region (5) without suffering leakage current.
摘要翻译：提供了具有固态图像传感器的半导体器件，其中不太可能发生漏电流。 P型半导体衬底（1）的表面部分易受到可能导致漏电流的各种缺陷的影响。因此，提供了N型掩埋沟道层（7a）。虽然在存在缺陷的P型半导体衬底（1）的表面附近的电位高，但是在由N型掩埋沟道层（7a）形成的PN结面附近，电位最小化，和P型半导体衬底（1）。因此，当转移开关（M1）被操作时，在该PN结面附近形成通道，从而可以将存储在光电二极管（PD）的N型源极区域（4a）中的电荷转移到没有漏电流的N型漏极区域（5）。

10. 发明授权

US5189498A Charge coupled device 失效
标题翻译：电荷耦合器件
公开(公告)号：US5189498A
公开(公告)日：1993-02-23
申请号：US608387
申请日：1990-11-02
申请人： Kiyohiko Sakakibara
发明人： Kiyohiko Sakakibara
IPC分类号： H01L29/10
CPC分类号： H01L29/1062
摘要： A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels. Therefore, the charges in the first horizontal channel can be transferred to the transfer channel by a gate voltage pinning the horizontal channel and the charges can be transferred from the first horizontal channel to the second horizontal channel by clock signals.
摘要翻译：电荷耦合器件包括第一导电类型半导体衬底中的第二导电类型的第一水平沟道，以及距离第一水平沟道预定距离的衬底中的第二导电类型的第二水平沟道;以及第二导电类型传输沟道，水平通道与第二水平通道，以使电荷能够从第一水平通道转移到第二水平通道。传输通道的钉扎电位的绝对值大于第一和第二水平通道的钉扎电位，并且固定传输沟道的栅极电压的绝对值小于固定第一和第二水平通道的栅极电压。因此，第一水平通道中的电荷可以通过锁定水平通道的栅极电压传送到传输通道，并且可以通过时钟信号将电荷从第一水平通道传送到第二水平通道。

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