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1. 发明申请

US20060073619A1 Semiconductor fabricating apparatus and method and apparatus for determining state of semiconductor fabricating process 审中-公开
标题翻译：用于确定半导体制造工艺的状态的半导体制造装置和方法和装置
公开(公告)号：US20060073619A1
公开(公告)日：2006-04-06
申请号：US11293213
申请日：2005-12-05
申请人： Tatehito Usui , Motohiko Yoshigai , Tsuyoshi Yoshida , Hideyuki Yamamoto
发明人： Tatehito Usui , Motohiko Yoshigai , Tsuyoshi Yoshida , Hideyuki Yamamoto
IPC分类号： H01L21/00 , H01L21/306 , C23F1/00
CPC分类号： H01J37/32935 , H01L21/31116
摘要： In a semiconductor device fabrication apparatus for performing an etching process for a semiconductor wafer having a plurality of films formed on a surface thereof and disposed in a chamber, by using plasma generated in the chamber, a change in light of multi-wavelength from the surface of the semiconductor wafer is measured during a predetermined period of the etching process, and a state of the etching process is judged from the displayed change amount of light of multi-wavelength.
摘要翻译：在半导体器件制造装置中，通过使用在室内产生的等离子体，对具有形成在其表面上的多个膜并且设置在室中的半导体晶片进行蚀刻处理，从表面的多波长的光的变化在蚀刻处理的预定周期期间测量半导体晶片，并且根据所显示的多波长的光的变化量来判断蚀刻处理的状态。

2. 发明授权

US06903826B2 Method and apparatus for determining endpoint of semiconductor element fabricating process 有权
标题翻译：用于确定半导体元件制造工艺的端点的方法和装置
公开(公告)号：US06903826B2
公开(公告)日：2005-06-07
申请号：US09946504
申请日：2001-09-06
申请人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
发明人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
IPC分类号： G01B11/06 , G01B9/02
CPC分类号： H01J37/32963 , G01B11/0675 , H01L22/26
摘要： Standard patterns of differential values of interference light that correspond to a predetermined step height of the first material being processed and standard patterns of differential values of interference light that correspond to a predetermined remaining mask layer thickness of the material are set. These standard patterns use wavelengths as parameters. Then, the intensities of interference light of multiple wavelengths are measured for a second material that has the same structure as the first material. Actual patterns with wavelength as parameter are determined from differential values of the measured interference light intensities. Based on the standard patterns and the actual patterns of the differential values, the step height and the remaining mask layer thickness of the second material are determined.
摘要翻译：对应于正在处理的第一材料的预定台阶高度的干涉光的差分值的标准图案和对应于材料的预定剩余掩模层厚度的干涉光的差分值的标准图案被设置。这些标准模式使用波长作为参数。然后，测量具有与第一材料相同结构的第二材料的多个波长的干涉光的强度。具有波长作为参数的实际图案由所测量的干涉光强度的差分值确定。基于标准图案和差分值的实际图案，确定第二材料的台阶高度和剩余掩模层厚度。

3. 发明授权

US07126697B2 Method and apparatus for determining endpoint of semiconductor element fabricating process 有权
公开(公告)号：US07126697B2
公开(公告)日：2006-10-24
申请号：US11340559
申请日：2006-01-27
申请人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
发明人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
IPC分类号： G01B11/02
CPC分类号： H01J37/32963 , G01B11/0675 , H01L22/26
摘要： Standard patterns of differential values of interference light that correspond to a predetermined step height of the first material being processed and standard patterns of differential values of interference light that correspond to a predetermined remaining mask layer thickness of the material are set. These standard patterns use wavelengths as parameters. Then, the intensities of interference light of multiple wavelengths are measured for a second material that has the same structure as the first material. Actual patterns with wavelength as parameter are determined from differential values of the measured interference light intensities. Based on the standard patterns and the actual patterns of the differential values, the step height and the remaining mask layer thickness of the second material are determined.

4. 发明申请

US20060132798A1 Method and apparatus for determining endpoint of semiconductor element fabricating process 有权
标题翻译：用于确定半导体元件制造工艺的端点的方法和装置
公开(公告)号：US20060132798A1
公开(公告)日：2006-06-22
申请号：US11340559
申请日：2006-01-27
申请人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
发明人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
IPC分类号： G01B11/02
CPC分类号： H01J37/32963 , G01B11/0675 , H01L22/26
摘要： Standard patterns of differential values of interference light that correspond to a predetermined step height of the first material being processed and standard patterns of differential values of interference light that correspond to a predetermined remaining mask layer thickness of the material are set. These standard patterns use wavelengths as parameters. Then, the intensities of interference light of multiple wavelengths are measured for a second material that has the same structure as the first material. Actual patterns with wavelength as parameter are determined from differential values of the measured interference light intensities. Based on the standard patterns and the actual patterns of the differential values, the step height and the remaining mask layer thickness of the second material are determined.
摘要翻译：对应于正在处理的第一材料的预定台阶高度的干涉光的差分值的标准图案和对应于材料的预定剩余掩模层厚度的干涉光的差分值的标准图案被设置。这些标准模式使用波长作为参数。然后，测量具有与第一材料相同结构的第二材料的多个波长的干涉光的强度。具有波长作为参数的实际图案由所测量的干涉光强度的差分值确定。基于标准图案和差分值的实际图案，确定第二材料的台阶高度和剩余掩模层厚度。

5. 发明授权

US07009715B2 Method and apparatus for determining endpoint of semiconductor element fabricating process and method and apparatus for processing member to be processed 有权
公开(公告)号：US07009715B2
公开(公告)日：2006-03-07
申请号：US10978412
申请日：2004-11-02
申请人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
发明人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
IPC分类号： G01B9/02
CPC分类号： H01J37/32963 , G01B11/0675 , H01L22/26
摘要： Standard patterns of differential values of interference light that correspond to a predetermined step height of the first material being processed and standard patterns of differential values of interference light that correspond to a predetermined remaining mask layer thickness of the material are set. These standard patterns use wavelengths as parameters. Then, the intensities of interference light of multiple wavelengths are measured for a second material that has the same structure as the first material. Actual patterns with wavelength as parameter are determined from differential values of the measured interference light intensities. Based on the standard patterns and the actual patterns of the differential values, the step height and the remaining mask layer thickness of the second material are determined.

6. 发明申请

US20050202575A1 Semiconductor fabricating apparatus and method and apparatus for determining state of semiconductor fabricating process 审中-公开
标题翻译：用于确定半导体制造工艺的状态的半导体制造装置和方法和装置
公开(公告)号：US20050202575A1
公开(公告)日：2005-09-15
申请号：US11126159
申请日：2005-05-11
申请人： Tatehito Usui , Motohiko Yoshigai , Tsuoyoshi Yoshida , Hideyuki Yamamoto
发明人： Tatehito Usui , Motohiko Yoshigai , Tsuoyoshi Yoshida , Hideyuki Yamamoto
IPC分类号： H01J37/32 , H01L21/311 , H01L21/66 , G01R31/26
CPC分类号： H01J37/32935 , H01L21/31116
摘要： In a semiconductor device fabrication apparatus for performing an etching process for a semiconductor wafer having a plurality of films formed on a surface thereof and disposed in a chamber, by using plasma generated in the chamber, a change in light of multi-wavelength from the surface of the semiconductor wafer is measured during a predetermined period of the etching process, and a state of the etching process is judged from the displayed change amount of light of multi-wavelength.
摘要翻译：在半导体器件制造装置中，通过使用在室内产生的等离子体，对具有形成在其表面上的多个膜并且设置在室中的半导体晶片进行蚀刻处理，从表面的多波长的光的变化在蚀刻处理的预定周期期间测量半导体晶片，并且根据所显示的多波长的光的变化量来判断蚀刻处理的状态。

7. 发明申请

US20050062982A1 Method and apparatus for determining endpoint of semiconductor element fabricating process and method and apparatus for processing member to be processed 有权
标题翻译：用于确定半导体元件制造工艺的端点的方法和装置以及用于处理待处理部件的方法和装置
公开(公告)号：US20050062982A1
公开(公告)日：2005-03-24
申请号：US10978412
申请日：2004-11-02
申请人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
发明人： Tatehito Usui , Takashi Fujii , Motohiko Yoshigai , Tetsunori Kaji , Hideyuki Yamamoto
IPC分类号： G01B11/06 , G01B9/02
CPC分类号： H01J37/32963 , G01B11/0675 , H01L22/26
摘要： Standard patterns of differential values of interference light that correspond to a predetermined step height of the first material being processed and standard patterns of differential values of interference light that correspond to a predetermined remaining mask layer thickness of the material are set. These standard patterns use wavelengths as parameters. Then, the intensities of interference light of multiple wavelengths are measured for a second material that has the same structure as the first material. Actual patterns with wavelength as parameter are determined from differential values of the measured interference light intensities. Based on the standard patterns and the actual patterns of the differential values, the step height and the remaining mask layer thickness of the second material are determined.
摘要翻译：对应于正在处理的第一材料的预定台阶高度的干涉光的差分值的标准图案和对应于材料的预定剩余掩模层厚度的干涉光的差分值的标准图案被设置。这些标准模式使用波长作为参数。然后，测量具有与第一材料相同结构的第二材料的多个波长的干涉光的强度。具有波长作为参数的实际图案由所测量的干涉光强度的差分值确定。基于标准图案和差分值的实际图案，确定第二材料的台阶高度和剩余掩模层厚度。

8. 发明授权

US08071397B2 Semiconductor fabricating apparatus with function of determining etching processing state 有权
标题翻译：具有确定蚀刻处理状态功能的半导体制造装置
公开(公告)号：US08071397B2
公开(公告)日：2011-12-06
申请号：US11840514
申请日：2007-08-17
申请人： Tatehito Usui , Motohiko Yoshigai , Kazuhiro Jyouo , Tetsuo Ono
发明人： Tatehito Usui , Motohiko Yoshigai , Kazuhiro Jyouo , Tetsuo Ono
IPC分类号： H01L21/00
CPC分类号： H01J37/32935 , H01L21/67069 , H01L21/67253
摘要： A semiconductor fabricating method including: placing the semiconductor wafer having a film thereon inside of a chamber; generating plasma; detecting a quantity of interference lights for each of at least two wavelengths obtained from a surface of the wafer for a predetermined time period during the etching of the wafer; detecting a first time point at which the detected quantity of interference lights for one of the two wavelengths becomes a maximum and a second time point at which the detected quantity of interference lights for the other wavelength becomes a minimum; determining a state of etching based on a result of comparing a predetermined value with an interval between the first and second time points, wherein both time points are detected by using outputs of a detector for detecting a quantity of the interference lights; and controlling etching in accordance with the determining.
摘要翻译：一种半导体制造方法，包括：将其上具有膜的半导体晶片放置在室内; 产生等离子体在晶片的蚀刻期间，在从晶片表面获得的每个至少两个波长的预定时间段内检测干涉光量; 检测所述检测到的两个波长中的一个波长的干扰光的检测量成为最大的第一时间点和所述其他波长的所检测的干涉光量成为最小的第二时间点; 基于将预定值与第一和第二时间点之间的间隔进行比较的结果来确定蚀刻状态，其中通过使用用于检测干涉光量的检测器的输出来检测两个时间点; 以及根据该确定来控制蚀刻。

9. 发明申请

US20070178610A1 Semiconductor Production Apparatus 审中-公开
标题翻译：半导体生产设备
公开(公告)号：US20070178610A1
公开(公告)日：2007-08-02
申请号：US11696878
申请日：2007-04-05
申请人： Tatehito Usui , Motohiko Yoshigai , Kazuhiro Joo , Shigeru Nakamoto
发明人： Tatehito Usui , Motohiko Yoshigai , Kazuhiro Joo , Shigeru Nakamoto
IPC分类号： H01L21/00 , H01L21/306 , C23F1/00 , H01L21/302
CPC分类号： H01J37/32972 , H01L21/32137
摘要： A semiconductor production apparatus and method for etching a semiconductor wafer arranged in a container and having a film on the surface thereof, by use of a plasma generated in the container. A temporal change of a quantity of an interference light is detected for at least two wavelengths obtained from the surface of the wafer for a predetermined time period of an etching process of the wafer, an etching quantity of the wafer is determined, which varies as long as the etching process proceeds, based upon a particular change arising in the interference light of plural pairs of wavelengths, the plural pairs of the wavelengths corresponding to the etching quantities, respectively.
摘要翻译：一种用于通过使用在容器中产生的等离子体来蚀刻布置在容器中并在其表面上具有膜的半导体晶片的半导体制造装置和方法。在晶片的蚀刻处理的预定时间段内，从晶片表面获得的至少两个波长检测干涉光量的时间变化，确定晶片的蚀刻量，其长度变化随着蚀刻工艺的进行，基于在多对波长的干涉光中产生的特定变化，分别对应于蚀刻量的多对波长。

10. 发明授权

US06972848B2 Semiconductor fabricating apparatus with function of determining etching processing state 有权
标题翻译：具有确定蚀刻处理状态功能的半导体制造装置
公开(公告)号：US06972848B2
公开(公告)日：2005-12-06
申请号：US10377823
申请日：2003-03-04
申请人： Tatehito Usui , Motohiko Yoshigai , Kazuhiro Jyouo , Tetsuo Ono
发明人： Tatehito Usui , Motohiko Yoshigai , Kazuhiro Jyouo , Tetsuo Ono
IPC分类号： G01B9/02 , G01R31/26 , H01J37/32
CPC分类号： H01J37/32935 , H01L21/67069 , H01L21/67253
摘要： When a semiconductor wafer placed in a chamber and having films thereon is etched using plasma generated in the chamber, a change in the amount of lights with at least two wavelengths, obtained from the wafer surface during the processing, is detected. The time between the time at which the amount of a light with one of two wavelengths is maximized and the time at which the amount of a light with the other wavelength is minimized is compared with a predetermined value to determine the state of etching processing.
摘要翻译：当使用在室中产生的等离子体来刻蚀放置在腔室中并且具有膜上的膜的半导体晶片时，检测在处理期间从晶片表面获得的具有至少两个波长的光量的变化。将具有两个波长中的一个的光量的时间最大化的时间与其他波长的光量最小化的时间与预定值进行比较，以确定蚀刻处理的状态。

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