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1. 发明授权

US08242013B2 Virtually substrate-less composite power semiconductor device and method 有权
标题翻译：几乎无衬底复合功率半导体器件及方法
公开(公告)号：US08242013B2
公开(公告)日：2012-08-14
申请号：US12749696
申请日：2010-03-30
申请人： Tao Feng , Yueh-Se Ho
发明人： Tao Feng , Yueh-Se Ho
IPC分类号： H01L21/4763
CPC分类号： H01L21/561 , H01L23/142 , H01L23/3114 , H01L23/49827 , H01L24/29 , H01L24/92 , H01L2224/29101 , H01L2224/2919 , H01L2224/8385 , H01L2224/9202 , H01L2224/94 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.
摘要翻译：公开了一种实际上无衬底的复合功率半导体器件（VSLCPSD）和方法。 VSLCPSD具有功率半导体器件（PSD），由载体材料制成的正面器件载体（FDC）和中间键合层（IBL）。载体和IBL材料都可以是导电的或不导电的。 PSD具有后衬底部分，具有图案化前面装置金属化焊盘的前半导体器件部分和实际上减小的厚度TPSD。 FDC具有接触前表面器件金属化焊盘，图案化前面载体金属化焊盘和多个并联连接的贯穿载体导电通孔的图案化背面载体金属化，其分别将背面载体金属化物连接到前面载体金属化焊盘。 FDC厚度TFDC足够大以向VSLCPSD提供结构刚度。厚度减小的TPSD会影响背面的底层电阻，并且贯穿载体的导电通孔会对前面装置的金属化焊盘产生低的前端接触电阻。

2. 发明申请

US20120104580A1 SUBSTRATELESS POWER DEVICE PACKAGES 有权
标题翻译：无底座动力装置包装
公开(公告)号：US20120104580A1
公开(公告)日：2012-05-03
申请号：US12916086
申请日：2010-10-29
申请人： Tao Feng , Zhiqiang Niu , Yuping Gong , Ruisheng Wu , Ping Huang , Lei Shi , Yueh-Se Ho
发明人： Tao Feng , Zhiqiang Niu , Yuping Gong , Ruisheng Wu , Ping Huang , Lei Shi , Yueh-Se Ho
IPC分类号： H01L23/495 , H01L23/498
CPC分类号： H01L21/6836 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/76897 , H01L21/78 , H01L23/3114 , H01L23/481 , H01L23/495 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/36 , H01L24/40 , H01L24/73 , H01L24/94 , H01L25/50 , H01L27/088 , H01L29/0657 , H01L29/7827 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04026 , H01L2224/04034 , H01L2224/05009 , H01L2224/05025 , H01L2224/051 , H01L2224/05139 , H01L2224/05155 , H01L2224/05166 , H01L2224/05571 , H01L2224/0603 , H01L2224/0616 , H01L2224/06181 , H01L2224/1184 , H01L2224/16245 , H01L2224/291 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/73253 , H01L2224/73255 , H01L2224/73263 , H01L2224/83801 , H01L2224/84801 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10253 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/2064 , H01L2924/3511 , H01L2224/03 , H01L2924/00 , H01L2224/05552 , H01L2924/00012 , H01L2224/37099
摘要： A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
摘要翻译：无基底复合功率半导体器件可以包括薄衬底和位于衬底顶表面上的顶金属层。衬底和外延层的总厚度可以小于25微米。焊料凸块形成在顶部金属层的顶部，并且模塑料围绕焊料凸起并且使焊料凸块至少部分暴露。

3. 发明授权

US07955893B2 Wafer level chip scale package and process of manufacture 有权
标题翻译：晶圆级芯片级封装及制造工艺
公开(公告)号：US07955893B2
公开(公告)日：2011-06-07
申请号：US12023921
申请日：2008-01-31
申请人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/00
CPC分类号： H01L29/7827 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/81 , H01L29/0657 , H01L29/41741 , H01L29/4175 , H01L29/45 , H01L29/49 , H01L29/7802 , H01L2224/02371 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要翻译：封装了功率晶圆级芯片级封装（CSP）和制造工艺。功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

4. 发明申请

US20080242052A1 Method of forming ultra thin chips of power devices 审中-公开
标题翻译：形成功率器件超薄芯片的方法
公开(公告)号：US20080242052A1
公开(公告)日：2008-10-02
申请号：US11694888
申请日：2007-03-30
申请人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , Francois Hebert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/30
CPC分类号： H01L21/3043 , H01L21/78
摘要： A method for making thin semiconductor devices is disclosed. Starting from wafer with pre-fabricated front-side devices, the method includes: Thinning wafer central portion from its back-side to produce a thin region while preserving original wafer thickness in the wafer periphery for structural strength. Forming ohmic contact at wafer back-side. Separating and collecting pre-fabricated devices. This further includes: Releasably bonding wafer back-side onto single-sided dicing tape, in turn supported by a dicing frame. Providing a backing plate to match the thinned out wafer central portion. Sandwiching the dicing tape between wafer and backing plate then pressing the dicing tape to bond with the wafer. With a step-profiled chuck to support wafer back-side, the pre-fabricated devices are separated from each other and from the wafer periphery in one dicing operation with dicing depth slightly thicker than the wafer central portion. The separated thin semiconductor devices are then picked up and collected.
摘要翻译：公开了制造薄半导体器件的方法。从具有预制的前端器件的晶片开始，该方法包括：从其背面将晶片中心部分变薄以产生薄区域，同时在晶片周边保留原始晶片厚度以获得结构强度。在晶圆背面形成欧姆接触。分离和收集预制设备。这还包括：将晶片背面可释放地粘合到单面切割胶带上，然后由切割架支撑。提供背板以匹配变薄的晶片中心部分。将切割胶带夹在晶片和背板之间，然后按压切割胶带与晶片结合。利用阶梯型卡盘来支撑晶片背面，在一个切割操作中，预制的装置彼此分离并且与晶片周边分离，切割深度比晶片中心部分稍厚。然后拾取并收集分离的薄半导体器件。

5. 发明申请

US20080182387A1 Method of fabricating a semiconductor device employing electroless plating 有权
标题翻译：使用化学镀的半导体器件的制造方法
公开(公告)号：US20080182387A1
公开(公告)日：2008-07-31
申请号：US11701561
申请日：2007-01-31
申请人： Tao Feng , Ming Sun , Yueh-Se Ho , Kai Liu
发明人： Tao Feng , Ming Sun , Yueh-Se Ho , Kai Liu
IPC分类号： H01L21/00
CPC分类号： H01L21/67132 , H01L21/288 , H01L21/6836 , H01L24/02 , H01L24/11 , H01L2221/68327 , H01L2224/0401 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014
摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.
摘要翻译：公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取从保护胶带上取下模具。

6. 发明授权

US08716063B2 Wafer level chip scale package and process of manufacture 有权
标题翻译：晶圆级芯片级封装及制造工艺
公开(公告)号：US08716063B2
公开(公告)日：2014-05-06
申请号：US13007356
申请日：2011-01-14
申请人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/00
CPC分类号： H01L29/7827 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/81 , H01L29/0657 , H01L29/41741 , H01L29/4175 , H01L29/45 , H01L29/49 , H01L29/7802 , H01L2224/02371 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要翻译：封装了功率晶圆级芯片级封装（CSP）和制造工艺。功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

7. 发明授权

US08426960B2 Wafer level chip scale packaging 有权
标题翻译：晶圆级芯片级封装
公开(公告)号：US08426960B2
公开(公告)日：2013-04-23
申请号：US11963690
申请日：2007-12-21
申请人： Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
发明人： Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
IPC分类号： H01L23/48
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/02 , H01L24/11 , H01L24/17 , H01L2221/68354 , H01L2224/0231 , H01L2224/0233 , H01L2224/0239 , H01L2224/0401 , H01L2224/04042 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.
摘要翻译：公开了一种用于在晶片级芯片级封装工艺中进行背对背电连接的方法。将包含多个半导体芯片的晶片安装在封装基板上。多个半导体芯片包括暴露背面的一个或多个电极。去除晶片上的两个或更多个相邻芯片之间的划痕线以形成较宽的间隙。将导电材料施加到半导体芯片的背面和间隙中。然后通过在两个或更多个芯片的背侧和侧壁上留下导电材料来切割两个或更多个芯片之间的间隙中的导电材料。结果，导电材料提供从芯片的背面上的电极到芯片的前侧的电连接。

8. 发明申请

US20110241214A1 Virtually Substrate-less Composite Power Semiconductor Device and Method 有权
标题翻译：几何无基板复合功率半导体器件及方法
公开(公告)号：US20110241214A1
公开(公告)日：2011-10-06
申请号：US12749696
申请日：2010-03-30
申请人： Tao Feng , Yueh-Se Ho
发明人： Tao Feng , Yueh-Se Ho
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/561 , H01L23/142 , H01L23/3114 , H01L23/49827 , H01L24/29 , H01L24/92 , H01L2224/29101 , H01L2224/2919 , H01L2224/8385 , H01L2224/9202 , H01L2224/94 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.
摘要翻译：公开了一种实际上无衬底的复合功率半导体器件（VSLCPSD）和方法。 VSLCPSD具有功率半导体器件（PSD），由载体材料制成的正面器件载体（FDC）和中间键合层（IBL）。载体和IBL材料都可以是导电的或不导电的。 PSD具有后衬底部分，具有图案化前面装置金属化焊盘的前半导体器件部分和实际上减小的厚度TPSD。 FDC具有接触前表面器件金属化焊盘，图案化前面载体金属化焊盘和多个并联连接的贯穿载体导电通孔的图案化背面载体金属化，其分别将背面载体金属化物连接到前面载体金属化焊盘。 FDC厚度TFDC足够大以向VSLCPSD提供结构刚度。厚度减小的TPSD会影响背面的底层电阻，并且贯穿载体的导电通孔会对前面装置的金属化焊盘产生低的前端接触电阻。

9. 发明申请

US20090321929A1 Standing chip scale package 有权
标题翻译：常规芯片级封装
公开(公告)号：US20090321929A1
公开(公告)日：2009-12-31
申请号：US12217136
申请日：2008-06-30
申请人： Tao Feng , Anup Bhalla , Yueh-Se Ho
发明人： Tao Feng , Anup Bhalla , Yueh-Se Ho
IPC分类号： H01L21/60 , H01L23/498
CPC分类号： H01L24/16 , H01L2224/05568 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/13099 , H01L2224/16 , H01L2224/32145 , H01L2224/73253 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/15153 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00014
摘要： A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.
摘要翻译：公开了一种立式芯片级封装。立式芯片级封装提供与芯片两侧的凸起器件触点的电连接。该封装可以以直立形式与印刷电路板耦合，使得凸起芯片的前侧和后侧基本上垂直于安装表面。还公开了制造立式芯片级封装的工艺。

10. 发明授权

US08987878B2 Substrateless power device packages 有权
标题翻译：无层无源功率器件封装
公开(公告)号：US08987878B2
公开(公告)日：2015-03-24
申请号：US12916086
申请日：2010-10-29
申请人： Tao Feng , Zhiqiang Niu , Yuping Gong , Ruisheng Wu , Ping Huang , Lei Shi , Yueh-Se Ho
发明人： Tao Feng , Zhiqiang Niu , Yuping Gong , Ruisheng Wu , Ping Huang , Lei Shi , Yueh-Se Ho
IPC分类号： H01L23/495 , H01L21/683 , H01L21/56 , H01L23/31 , H01L23/48 , H01L23/00 , H01L29/06
CPC分类号： H01L21/6836 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/6835 , H01L21/76897 , H01L21/78 , H01L23/3114 , H01L23/481 , H01L23/495 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/36 , H01L24/40 , H01L24/73 , H01L24/94 , H01L25/50 , H01L27/088 , H01L29/0657 , H01L29/7827 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04026 , H01L2224/04034 , H01L2224/05009 , H01L2224/05025 , H01L2224/051 , H01L2224/05139 , H01L2224/05155 , H01L2224/05166 , H01L2224/05571 , H01L2224/0603 , H01L2224/0616 , H01L2224/06181 , H01L2224/1184 , H01L2224/16245 , H01L2224/291 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/73253 , H01L2224/73255 , H01L2224/73263 , H01L2224/83801 , H01L2224/84801 , H01L2224/94 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10253 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/2064 , H01L2924/3511 , H01L2224/03 , H01L2924/00 , H01L2224/05552 , H01L2924/00012 , H01L2224/37099
摘要： A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.
摘要翻译：无基底复合功率半导体器件可以包括薄衬底和位于衬底顶表面上的顶金属层。衬底和外延层的总厚度可以小于25微米。焊料凸块形成在顶部金属层的顶部，并且模塑料围绕焊料凸起并且使焊料凸块至少部分暴露。

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