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2. 发明授权

US07240144B2 Arbitration of data transfer requests 有权
标题翻译：仲裁数据传输请求
公开(公告)号：US07240144B2
公开(公告)日：2007-07-03
申请号：US10815961
申请日：2004-04-02
申请人： Tan Ba Tran , Gerard Richard Williams , David Terrence Matheny , David Walter Flynn
发明人： Tan Ba Tran , Gerard Richard Williams , David Terrence Matheny , David Walter Flynn
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/28
摘要： A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with said data processor core; a data processing portion 12 operable to perform data processing operations; a read/write port 40 operable to transfer data from said processor core to at least two buses 75A, 75B said at least two buses being operable to provide data communication between said processor core 10 and said at least one memory 120, said at least one memory 120 comprising at least two portions 120A, 120B, each of said at least two buses 75A, 75B being operable to provide data access to respective ones of said at least two portions 120A, 120B; arbitration logic 110 associated with said read/write port 40; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.
摘要翻译：一种数据处理器核心10，包括：存储器访问接口部分30，可操作以在外部数据源与与所述数据处理器核心相关联的至少一个存储器120之间执行数据传输操作; 数据处理部分12，用于执行数据处理操作; 读/写端口40，其可操作以将数据从所述处理器核传输到至少两个总线75A，75B，所述至少两个总线可操作以在所述处理器核心10和所述至少一个存储器120之间提供数据通信，至少一个存储器120包括至少两个部分120A，120B，所述至少两个总线75A，75B中的每一个可操作以提供对所述至少两个部分120A，120B中的相应部分的数据访问; 与所述读/写端口40相关联的仲裁逻辑110; 其中所述仲裁逻辑可操作用于将请求数据访问的数据访问请求路由到从所述存储器访问接口接收的所述至少一个存储器的一部分中的数据访问到所述至少两个总线之一，提供对所述至少一个的所述一个部分的访问存储器，并且路由进一步的数据访问请求，请求从所述数据处理部分接收的所述至少一个存储器的另一部分中的数据访问到所述至少两个总线中的另一个，提供对所述至少一个存储器，所述数据访问请求的路由在相同的时钟周期期间执行。

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