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1. 发明授权

US07216274B2 Flexible scan architecture 有权
标题翻译：灵活的扫描架构
公开(公告)号：US07216274B2
公开(公告)日：2007-05-08
申请号：US10609254
申请日：2003-06-26
申请人： Talal K. Jaber , Srinivas Patil , Larry E. Thatcher , Chih-Jen M. Lin , Anil K. Sabbavarapu , David M. Wu , Madhukar K. Reddy
发明人： Talal K. Jaber , Srinivas Patil , Larry E. Thatcher , Chih-Jen M. Lin , Anil K. Sabbavarapu , David M. Wu , Madhukar K. Reddy
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/318594 , G06F11/2236
摘要： A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.
摘要翻译：用于测试复杂集成电路的测试架构，其中每个功能单元可以独立于其他功能单元进行测试。本发明的实施例允许功能单元的测试以比处理器的其它部分更慢或更快的时钟速度发生，而不会引起延迟或其他不利的定时效应。

2. 发明授权

US06815977B2 Scan cell systems and methods 失效
标题翻译：扫描细胞系统和方法
公开(公告)号：US06815977B2
公开(公告)日：2004-11-09
申请号：US10328203
申请日：2002-12-23
申请人： Anil K. Sabbavarapu , Talal K. Jaber , Grant W. McFarland , Paven R. Sunkerneni , David M. Wu
发明人： Anil K. Sabbavarapu , Talal K. Jaber , Grant W. McFarland , Paven R. Sunkerneni , David M. Wu
IPC分类号： H03K1900
CPC分类号： G01R31/318541 , G01R31/318552
摘要： According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.
摘要翻译：根据一些实施例，电路包括Domino状态元件，主锁存器，用于接收第一时钟信号并且响应于第一时钟信号在Domino状态元件中存储值;以及从锁存器，用于接收第二时钟信号并且响应于第二时钟信号而输出该值。一些实施例提供耦合到第一节点的第一状态单元，耦合到第一状态单元的主锁存器，主锁存器以接收第一存储信号，第一负载信号，第一时钟信号和第一扫描值信号，耦合到第二节点的第二状态元件，连接到第一节点的第二节点和耦合到第二状态元件的从锁存器，从锁存器接收第二存储信号，第二负载信号，第二时钟信号和第二扫描值信号。

3. 发明授权

US07437634B2 Test scan cells 有权
标题翻译：测试扫描单元格
公开(公告)号：US07437634B2
公开(公告)日：2008-10-14
申请号：US10436775
申请日：2003-05-13
申请人： Talal K. Jaber , Anil K. Sabbavarapu
发明人： Talal K. Jaber , Anil K. Sabbavarapu
IPC分类号： G01R31/28 , H03K3/289
CPC分类号： G01R31/318541 , G01R31/318552
摘要： A sequential scan cell includes an input port for functional data and an input for scan test data. The input for scan test data is an input to a master scan flip-flop coupled to a slave scan flip-flop defining a scan test circuit. Such a scan test circuit is coupled to the functional circuit of the sequential scan cell such that the path for a functional signal is not through the scan test circuit, imparting no performance penalty to the functional signal. Scan test data is scanned in and out of the sequential cell by two non-overlapping scan clocks that are active only when system functional clocks are in an off state.
摘要翻译：顺序扫描单元包括用于功能数据的输入端口和用于扫描测试数据的输入端。用于扫描测试数据的输入是耦合到定义扫描测试电路的从扫描触发器的主扫描触发器的输入。这种扫描测试电路耦合到顺序扫描单元的功能电路，使得功能信号的路径不通过扫描测试电路，对功能信号不施加任何性能损失。扫描测试数据通过两个非重叠的扫描时钟扫描顺序单元格，并且仅在系统功能时钟处于关闭状态时处于活动状态。

4. 发明申请

US20110161759A1 SCAN ARCHITECTURE AND DESIGN METHODOLOGY YIELDING SIGNIFICANT REDUCTION IN SCAN AREA AND POWER OVERHEAD 有权
标题翻译：扫描架构和设计方法在扫描区域和功率范围内的重要性降低
公开(公告)号：US20110161759A1
公开(公告)日：2011-06-30
申请号：US12648812
申请日：2009-12-29
申请人： Talal K. Jaber , David M. Wu
发明人： Talal K. Jaber , David M. Wu
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318575 , G01R31/318541
摘要： A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.
摘要翻译：通常会提供扫描结构和设计方法，显着减少扫描面积和功耗开销。在这方面，引入了包括多个组合逻辑云，与组合逻辑云耦合的扫描单元，扫描单元以加载测试向量的装置，其中扫描单元包括多个第一类型扫描单元和第二类型扫描单元与单独的组合逻辑云输出顺序耦合，以及第一扫描时钟和第二扫描时钟，其中第一扫描时钟控制第一类扫描单元，第二扫描时钟控制第二类扫描单元。还描述和要求保护其他实施例。

5. 发明授权

US08321730B2 Scan architecture and design methodology yielding significant reduction in scan area and power overhead 有权
标题翻译：扫描架构和设计方法可显着降低扫描面积和功耗
公开(公告)号：US08321730B2
公开(公告)日：2012-11-27
申请号：US12648812
申请日：2009-12-29
申请人： Talal K. Jaber , David M. Wu
发明人： Talal K. Jaber , David M. Wu
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318575 , G01R31/318541
摘要： A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.
摘要翻译：通常会提供扫描结构和设计方法，显着减少扫描面积和功耗开销。在这方面，引入了包括多个组合逻辑云，与组合逻辑云耦合的扫描单元，扫描单元以加载测试向量的装置，其中扫描单元包括多个第一类型扫描单元和第二类型扫描单元与单独的组合逻辑云输出顺序耦合，以及第一扫描时钟和第二扫描时钟，其中第一扫描时钟控制第一类扫描单元，第二扫描时钟控制第二类扫描单元。还描述和要求保护其他实施例。

6. 发明授权

US5614838A Reduced power apparatus and method for testing high speed components 失效
标题翻译：用于测试高速组件的低功率设备和方法
公开(公告)号：US5614838A
公开(公告)日：1997-03-25
申请号：US552661
申请日：1995-11-03
申请人： Talal K. Jaber , Steven A. Schmidt
发明人： Talal K. Jaber , Steven A. Schmidt
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G04F4/00
CPC分类号： G01R31/318577 , G01R31/2815 , G01R31/31721 , G01R31/318552
摘要： A system for testing a high speed integrated circuit includes a test device having a test clock with a first maximum frequency for performing level sensitive scan design (LSSD) testing of the integrated circuit device under test, a frequency multiplier circuit for multiplying the test clock signal to a higher second frequency capable of operating the device under test, and a finite state machine for generating a first internal clock for testing the device under test. In a practical embodiment, the internal clock speed may be running at a frequency many multiples of the test clock. Alternatively, a method of testing a device under test (DUT) at design speed includes running a predetermined group of tests with a test device operating at a lower speed than the design speed; incorporating LSSD or boundary scan test techniques in the device under test, together with a frequency multiplying device; generating a global clock for the device under test from the frequency multiplying circuit and using a finite state machine as a synchronizer and pulse generator to control a capture clock with respect to the global clock.
摘要翻译：一种用于测试高速集成电路的系统，包括具有测试时钟的测试装置，该测试时钟具有用于对被测集成电路装置进行电平敏感扫描设计（LSSD）测试的第一最大频率，用于将测试时钟信号到能够操作被测器件的较高的第二频率，以及用于产生用于测试被测器件的第一内部时钟的有限状态机。在实际实施例中，内部时钟速度可以以测试时钟的许多倍的频率运行。或者，以设计速度测试被测设备（DUT）的方法包括以比设计速度更低的速度操作的测试设备运行预定组的测试; 将LSSD或边界扫描测试技术与被测设备一起，并配有一个倍频装置; 从倍频电路产生被测器件的全局时钟，并使用有限状态机作为同步器和脉冲发生器来控制相对于全局时钟的捕获时钟。

7. 发明授权

US07028239B2 Microprocessor on-chip testing architecture and implementation 失效
公开(公告)号：US07028239B2
公开(公告)日：2006-04-11
申请号：US09751750
申请日：2000-12-29
申请人： Talal K. Jaber
发明人： Talal K. Jaber
IPC分类号： G01R31/28
CPC分类号： G06F11/263 , G01R31/31813
摘要： A method and apparatus are presented for on-chip testing of circuits in testing channels. In an embodiment of the present invention, the system includes a weight selector that allows for a wide variety of weighting of test data that is to be supplied to the testing channels. For example, the weight selector may be used to weight all bits in all channels or individual bits in a particular channel. Clock control and diagnostic logic may also be provided to selectively supply scan, functional, and/or stop clock signals to the testing channels. Channel filtering logic may be also provided to mask output data from a selected testing channel as desired. The method and apparatus may provide improved testing performance and power savings.

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